CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 82.
22. lappuse
approximate Computation approximate approximate cycle - accurate cycle - accurate wire Table 1 : Characteristics of different abstraction models Extending the SystemC Synthesis Subset by Object - Oriented Features. Models Specification ...
approximate Computation approximate approximate cycle - accurate cycle - accurate wire Table 1 : Characteristics of different abstraction models Extending the SystemC Synthesis Subset by Object - Oriented Features. Models Specification ...
62. lappuse
... computation will go on using the vector presentation . Using the GF multiplier instead of the look up tables will speed up total application , as now we are able to multiply two GF elements and get the result in one clock cycle ...
... computation will go on using the vector presentation . Using the GF multiplier instead of the look up tables will speed up total application , as now we are able to multiply two GF elements and get the result in one clock cycle ...
148. lappuse
... compute the search cost of an algorithm in terms of the number of times list scheduling is applied to the original graph . The computation cost of STDu algorithm can be estimated as the summation of unfolding cost ( Cuf ) and scheduling ...
... compute the search cost of an algorithm in terms of the number of times list scheduling is applied to the original graph . The computation cost of STDu algorithm can be estimated as the summation of unfolding cost ( Cuf ) and scheduling ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires