CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 14.
97. lappuse
... compression technique for reducing the size of loop memory has enabled a single - chip low - cost realization of the encoder . In the architectural front ... Compression 2. ALGORITHM Compression yields a compact representation of a signal 97.
... compression technique for reducing the size of loop memory has enabled a single - chip low - cost realization of the encoder . In the architectural front ... Compression 2. ALGORITHM Compression yields a compact representation of a signal 97.
98. lappuse
... compression [ 7 ] , wherein the loop memory is in the DCT domain and the DCT coefficients are stored using a scalable bit - plane based zonal coding approach . Figure 1 ( b ) depicts a video encoder with embedded compression for the ...
... compression [ 7 ] , wherein the loop memory is in the DCT domain and the DCT coefficients are stored using a scalable bit - plane based zonal coding approach . Figure 1 ( b ) depicts a video encoder with embedded compression for the ...
102. lappuse
... compression and the CPU- and loop memories in the case with embedded compression . While the loop memory has been embedded on - chip in the second case , the size of the motion estimation processor and texture processor have been ...
... compression and the CPU- and loop memories in the case with embedded compression . While the loop memory has been embedded on - chip in the second case , the size of the motion estimation processor and texture processor have been ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires