CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 63.
152. lappuse
... components and on the interaction between them . SEAS uses a simulation - based approach in order to account for dynamic effects such as bus contention , buffer overflows , etc. These effects depend on the performance of individual ...
... components and on the interaction between them . SEAS uses a simulation - based approach in order to account for dynamic effects such as bus contention , buffer overflows , etc. These effects depend on the performance of individual ...
174. lappuse
... Components ( battery capacity = 19278 Joules ) . Energy / day ( J / day ) Lifetime eBlocks PIC HW Button 2.722 0 Light Sensor 2.722 44.5 LED 2.678 14.4 20 years 1 year 3 years Green / Red LED 2.678 28.8 2 years Beeper 2.678 27 2 years 2 ...
... Components ( battery capacity = 19278 Joules ) . Energy / day ( J / day ) Lifetime eBlocks PIC HW Button 2.722 0 Light Sensor 2.722 44.5 LED 2.678 14.4 20 years 1 year 3 years Green / Red LED 2.678 28.8 2 years Beeper 2.678 27 2 years 2 ...
198. lappuse
... components , we only increase the number n by 1 . We performed a preliminary experiment to compare the accuracy of the base model and that of the modified model . In this experiment , the number of processing components is set to 10 and ...
... components , we only increase the number n by 1 . We performed a preliminary experiment to compare the accuracy of the base model and that of the modified model . In this experiment , the number of processing components is set to 10 and ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires