CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 46.
13. lappuse
... complexity of the architectures demands high performance simulation , the increasing variety of available architectures makes retargetability a critical feature of an instruction - set simulator . Retargetability requires generic models ...
... complexity of the architectures demands high performance simulation , the increasing variety of available architectures makes retargetability a critical feature of an instruction - set simulator . Retargetability requires generic models ...
55. lappuse
... Complexity Analysis Table 3 shows the complexity figures of the SWP GF ( 2 TM ) arithmetic circuits in terms of P and Q. The size of the arithmetic circuits without modification are comparable to that outlined in [ 9 , 10 ] , which is ...
... Complexity Analysis Table 3 shows the complexity figures of the SWP GF ( 2 TM ) arithmetic circuits in terms of P and Q. The size of the arithmetic circuits without modification are comparable to that outlined in [ 9 , 10 ] , which is ...
200. lappuse
... complexity of the LP ( linear program ) solver is pseudo - polynomial , the overall time complexity is also pseudo - polynomial . Table 4 confirms this fact that the proposed technique has acceptable complexity for design space ...
... complexity of the LP ( linear program ) solver is pseudo - polynomial , the overall time complexity is also pseudo - polynomial . Table 4 confirms this fact that the proposed technique has acceptable complexity for design space ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires