CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 33.
8. lappuse
... complex and heterogeneous communication schemes . The following section discusses related work in the area of explo- ration of system level communication architectures . After that the projected design flow followed by the technical ...
... complex and heterogeneous communication schemes . The following section discusses related work in the area of explo- ration of system level communication architectures . After that the projected design flow followed by the technical ...
13. lappuse
... complex instruction formats requires extensive coding in this language . In contrast , our simulation framework efficiently supports a wide variety of instruction formats supported by contemporary processor architectures as well as ...
... complex instruction formats requires extensive coding in this language . In contrast , our simulation framework efficiently supports a wide variety of instruction formats supported by contemporary processor architectures as well as ...
182. lappuse
... complex for making intuitive decisions at an early design stage where the de- sign space is very large . Likely , these systems will even get more complex in the near future . Besides , there exist multiple criteria to consider , like ...
... complex for making intuitive decisions at an early design stage where the de- sign space is very large . Likely , these systems will even get more complex in the near future . Besides , there exist multiple criteria to consider , like ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
19 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires