CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 28.
88. lappuse
... complete heuristic . The results are presented in Figure 11 , which shows the percentage of schedulable applications ( relative to the total number of applica- tions ) that have been produced by each optimization step . For ex- ample ...
... complete heuristic . The results are presented in Figure 11 , which shows the percentage of schedulable applications ( relative to the total number of applica- tions ) that have been produced by each optimization step . For ex- ample ...
103. lappuse
... complete Wideband CDMA ( WCDMA ) digital receiver part of an AMR channel onto a reconfigurable core . WCDMA is one of the two major standards for the third generation ( 3G ) cellular systems . Traditionally most of the receiver ...
... complete Wideband CDMA ( WCDMA ) digital receiver part of an AMR channel onto a reconfigurable core . WCDMA is one of the two major standards for the third generation ( 3G ) cellular systems . Traditionally most of the receiver ...
121. lappuse
... complete the application before the deadline . On the other hand , most of the time only a few of the 5 task graphs are active and hence DVS can be applied to save energy . The on- line inter - task DVS algorithm [ 19 ] , which is ...
... complete the application before the deadline . On the other hand , most of the time only a few of the 5 task graphs are active and hence DVS can be applied to save energy . The on- line inter - task DVS algorithm [ 19 ] , which is ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires