CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 58.
112. lappuse
... compared with ROCM - 32 and ROCM - 128 . 0.007 Synthesis of Real - Time Embedded Software with Local and. Proc / Mem Interface ARM7 MEM Tautology.1 SetLit Min . Coproc . DoesInter Cofactor.1 data addr 4. Results ( a ) While our main ...
... compared with ROCM - 32 and ROCM - 128 . 0.007 Synthesis of Real - Time Embedded Software with Local and. Proc / Mem Interface ARM7 MEM Tautology.1 SetLit Min . Coproc . DoesInter Cofactor.1 data addr 4. Results ( a ) While our main ...
113. lappuse
... compared with ROCM - 32 and ROCM - 128 . We calculated the energy required for ROCM - 32 , ROCM - 128 , and our codesigned minimizers we used the following set of equations : Although the minimization coprocessors required up to an ...
... compared with ROCM - 32 and ROCM - 128 . We calculated the energy required for ROCM - 32 , ROCM - 128 , and our codesigned minimizers we used the following set of equations : Although the minimization coprocessors required up to an ...
227. lappuse
... compared to SPECint benchmark . The reason is that the protocol processing is more like a streamlined process- ing with only a small number of loops . These program properties require different cache configurations compared to SPECint ...
... compared to SPECint benchmark . The reason is that the protocol processing is more like a streamlined process- ing with only a small number of loops . These program properties require different cache configurations compared to SPECint ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires