CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 91.
8. lappuse
... communication models . Instead , we address the early exploration and profiling driven partitioning of large - scale systems with complex and heterogeneous communication schemes . The following section discusses related work in the area ...
... communication models . Instead , we address the early exploration and profiling driven partitioning of large - scale systems with complex and heterogeneous communication schemes . The following section discusses related work in the area ...
12. lappuse
... communication models , while the functional units are reused by means of adapters bridging the dif- ferent levels of abstraction . The comparison of packet - based and cycle accurate communication revealed , that the simulation accu ...
... communication models , while the functional units are reused by means of adapters bridging the dif- ferent levels of abstraction . The comparison of packet - based and cycle accurate communication revealed , that the simulation accu ...
99. lappuse
... communication , bit- and cycle - true functional models for software processing tasks , behavioral models for hardware processing tasks . e ) Partially implemented cycle - true hardware level ; bit- and cycle - true models for the ...
... communication , bit- and cycle - true functional models for software processing tasks , behavioral models for hardware processing tasks . e ) Partially implemented cycle - true hardware level ; bit- and cycle - true models for the ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires