CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 44.
68. lappuse
... clock frequency rates required to run the described command and control task in real - time on state of the art as well as future or extended PDAs . 7. PERFORMANCE EVALUATIONS We compiled Sonic's code under three levels of optimization ...
... clock frequency rates required to run the described command and control task in real - time on state of the art as well as future or extended PDAs . 7. PERFORMANCE EVALUATIONS We compiled Sonic's code under three levels of optimization ...
76. lappuse
... clock cycles and allows to drive long wires with the same clock signal used to control short wires and logic gates . An alternative to wire pipelining is to drive long wires with slower clocks , thus effectively implement- ing the chip ...
... clock cycles and allows to drive long wires with the same clock signal used to control short wires and logic gates . An alternative to wire pipelining is to drive long wires with slower clocks , thus effectively implement- ing the chip ...
77. lappuse
... clock cycles are still needed to go from corner - to- corner for the die of 28.3mmx28.3mm in the 0.07μm technology generation , assuming a 5.63GHz clock by 2006 predicted in ITRS'01 [ 5 ] . This clearly suggests that multi - cycle on ...
... clock cycles are still needed to go from corner - to- corner for the die of 28.3mmx28.3mm in the 0.07μm technology generation , assuming a 5.63GHz clock by 2006 predicted in ITRS'01 [ 5 ] . This clearly suggests that multi - cycle on ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires