CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 43.
54. lappuse
... circuits of the GF ( 2 ) processor forms the middle abstraction level in Table 1 in this paper . An Instruction Set ... circuit allows the processor to compute P GF ( 2 " ) arithmetic operations ( n ≤Q ) or one GF ( 2 " ) arithmetic ...
... circuits of the GF ( 2 ) processor forms the middle abstraction level in Table 1 in this paper . An Instruction Set ... circuit allows the processor to compute P GF ( 2 " ) arithmetic operations ( n ≤Q ) or one GF ( 2 " ) arithmetic ...
55. lappuse
... circuit . The added propagation delay due to the configuration circuits for multiplication and division corresponds to TMUX2 and to TMUX2 + TMUXQ respectively . ( Note : TMUXI is the propagation delay through an i - input multiplexor ...
... circuit . The added propagation delay due to the configuration circuits for multiplication and division corresponds to TMUX2 and to TMUX2 + TMUXQ respectively . ( Note : TMUXI is the propagation delay through an i - input multiplexor ...
166. lappuse
... circuits ( adsl , eel , con ) are illustrated in figure 6 , all shown with same y - axis range ( 0.06 to -0.02mA ) . The adsl and eel adiabatic circuits clearly showed a lower DPA characteristic than the same circuit using conventional ...
... circuits ( adsl , eel , con ) are illustrated in figure 6 , all shown with same y - axis range ( 0.06 to -0.02mA ) . The adsl and eel adiabatic circuits clearly showed a lower DPA characteristic than the same circuit using conventional ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires