CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 75.
75. lappuse
... chip , will drive the design process . Interconnect latency will have a major impact on the de- sign of on - chip communication architectures , which increasingly rely on wire pipelining to go beyond the capabilities of traditional wire ...
... chip , will drive the design process . Interconnect latency will have a major impact on the de- sign of on - chip communication architectures , which increasingly rely on wire pipelining to go beyond the capabilities of traditional wire ...
109. lappuse
... chip greatly reduces system complexity and security versus an approach that involves communication with a desktop logic minimizer . An on - chip minimizer must be exceptionally lean yet yield good enough results . Previous software ...
... chip greatly reduces system complexity and security versus an approach that involves communication with a desktop logic minimizer . An on - chip minimizer must be exceptionally lean yet yield good enough results . Previous software ...
156. lappuse
... chip also has a fixed set of programmable hardware elements that are much more closely coupled than for systems in the large . New application types will require the chip to be considered programmable along with the individual ...
... chip also has a fixed set of programmable hardware elements that are much more closely coupled than for systems in the large . New application types will require the chip to be considered programmable along with the individual ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires