CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 48.
9. lappuse
... Channel Structure After the transactions are processed by the network engine , the respective TDS is passed back to the NoC Channel with an attached tag . This tag denotes the calculated arrival time of the transaction . According to ...
... Channel Structure After the transactions are processed by the network engine , the respective TDS is passed back to the NoC Channel with an attached tag . This tag denotes the calculated arrival time of the transaction . According to ...
21. lappuse
... channels have estimated approximate time , which is speci- fied in the channels by one wait statement per transaction . Because several channels may be grouped to one abstract bus channel , two parameters are added to the interface func ...
... channels have estimated approximate time , which is speci- fied in the channels by one wait statement per transaction . Because several channels may be grouped to one abstract bus channel , two parameters are added to the interface func ...
185. lappuse
... channels . For this gene , the second Kahn process is mapped onto DSP2 while the second FIFO channel is mapped onto DRAM . We also see that the allele sets for these two genes are different . 3.2 Constraint Violation We have developed a ...
... channels . For this gene , the second Kahn process is mapped onto DSP2 while the second FIFO channel is mapped onto DRAM . We also see that the allele sets for these two genes are different . 3.2 Constraint Violation We have developed a ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires