CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 44.
60. lappuse
... called TinyRISC , an array of 64 Reconfigurable Cells ( RCs ) organized in SIMD fashion , and a special data movement unit called Frame Buffer ( FB ) . The programming model is simple . TinyRISC takes charge of the whole Data Control ...
... called TinyRISC , an array of 64 Reconfigurable Cells ( RCs ) organized in SIMD fashion , and a special data movement unit called Frame Buffer ( FB ) . The programming model is simple . TinyRISC takes charge of the whole Data Control ...
95. lappuse
... called Code Generation . In this sub - step an executable code of a Kahn process network is generated from the PN model . We use a soft- ware engineering technique called Visitor to visit the PN model structure and to generate the ...
... called Code Generation . In this sub - step an executable code of a Kahn process network is generated from the PN model . We use a soft- ware engineering technique called Visitor to visit the PN model structure and to generate the ...
104. lappuse
... called the RC Array , and a 32 - bit RISC processor , called the mRISC ( Figure 1 ) . The RC Array consists of Reconfigurable Cells ( RCs ) interconnected by a reconfigurable network . Both the functionality of the RCs and the network ...
... called the RC Array , and a 32 - bit RISC processor , called the mRISC ( Figure 1 ) . The RC Array consists of Reconfigurable Cells ( RCs ) interconnected by a reconfigurable network . Both the functionality of the RCs and the network ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires