CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 17.
133. lappuse
... caching the entire row of 1024 bytes , caching array b in contrast does not provide any performance benefits . In fact , since there is no spatial reuse of the cached line , caching the entire row of b wastes energy in the on - memory cache ...
... caching the entire row of 1024 bytes , caching array b in contrast does not provide any performance benefits . In fact , since there is no spatial reuse of the cached line , caching the entire row of b wastes energy in the on - memory cache ...
214. lappuse
... cache line containing the object immediately after executing this instruction . After these three optimization strategies , we focus our attention on object access times and show that it is beneficial to turn - off cache lines ...
... cache line containing the object immediately after executing this instruction . After these three optimization strategies , we focus our attention on object access times and show that it is beneficial to turn - off cache lines ...
215. lappuse
... cache line . Further , these multiple objects can be in different phases of their lives . For example , two objects can share a cache line , and one of them might be live ( i.e. , its last use has not been reached yet ) , whereas the ...
... cache line . Further , these multiple objects can be in different phases of their lives . For example , two objects can share a cache line , and one of them might be live ( i.e. , its last use has not been reached yet ) , whereas the ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires