CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 28.
29. lappuse
... Buffer ; void producerOdd ( ) { int val ; shared Buffer.reset ( ) ; sharedBuffer.subscribe ( ) ; val = 1 ; wait ( ) ; while ( true ) { // Blocking global method call to ' shared Buffer ' : GLOBAL PROCEDURE.CALL ( shared Buffer , put ...
... Buffer ; void producerOdd ( ) { int val ; shared Buffer.reset ( ) ; sharedBuffer.subscribe ( ) ; val = 1 ; wait ( ) ; while ( true ) { // Blocking global method call to ' shared Buffer ' : GLOBAL PROCEDURE.CALL ( shared Buffer , put ...
99. lappuse
... buffer memory is allocated at set - up and is reused during operation . Therefore , we need primitives to get and put buffer memory space . On the data producing side we want to get emptied token buffers and put full buffers . On the ...
... buffer memory is allocated at set - up and is reused during operation . Therefore , we need primitives to get and put buffer memory space . On the data producing side we want to get emptied token buffers and put full buffers . On the ...
180. lappuse
... buffer we checked the following properties : Property 1 The implementation of the handshake protocol includes a finite size FIFO buffer . It is obvious that any higher data rate of input values than the buffer size was dimensioned for ...
... buffer we checked the following properties : Property 1 The implementation of the handshake protocol includes a finite size FIFO buffer . It is obvious that any higher data rate of input values than the buffer size was dimensioned for ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires