CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 82.
101. lappuse
... block is motion estimated for all the candidate motion vectors in order to determine the best matching motion vector . Further , optionally , this best vector can be refined to half / quarter pixel accuracy . The 3DRS motion estimation ...
... block is motion estimated for all the candidate motion vectors in order to determine the best matching motion vector . Further , optionally , this best vector can be refined to half / quarter pixel accuracy . The 3DRS motion estimation ...
172. lappuse
... Block - Light Sensor eBlock ( b ) Communication / Logic Block - 2 - Input Logic eBlock ( c ) Output Block - Green / Red LED eBlock ( a ) IX rx ( b ) 4.2 Computers in Every Block ( c ) We quickly determined that communication of logic ...
... Block - Light Sensor eBlock ( b ) Communication / Logic Block - 2 - Input Logic eBlock ( c ) Output Block - Green / Red LED eBlock ( a ) IX rx ( b ) 4.2 Computers in Every Block ( c ) We quickly determined that communication of logic ...
203. lappuse
... block B , we define genB = [ mo , ... , mn - 1 ] where mi = m if m is the first memory block in B that maps to cache block i and if no memory block in B maps to cache block i . The iterative equations are as follows : LCSB SOUT = U ...
... block B , we define genB = [ mo , ... , mn - 1 ] where mi = m if m is the first memory block in B that maps to cache block i and if no memory block in B maps to cache block i . The iterative equations are as follows : LCSB SOUT = U ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
19 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires