CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 89.
83. lappuse
... approaches for handling tasks in real - time appli- cations [ 7 ] . In the event - triggered approach ( ET ) , activities are initi- ated whenever a particular event is noted . In the time - triggered ( TT ) approach , activities are ...
... approaches for handling tasks in real - time appli- cations [ 7 ] . In the event - triggered approach ( ET ) , activities are initi- ated whenever a particular event is noted . In the time - triggered ( TT ) approach , activities are ...
91. lappuse
... approach . 1.1 Paper Contributions We present a novel systematic and step - wise approach that al- lows automatic derivation of executable Process Network specifi- cations from Weakly Dynamic Applications . New notions like Dy- namic ...
... approach . 1.1 Paper Contributions We present a novel systematic and step - wise approach that al- lows automatic derivation of executable Process Network specifi- cations from Weakly Dynamic Applications . New notions like Dy- namic ...
96. lappuse
4. RESULTS Most of the steps in our approach , presented in Section 2 and Section 3 , have been implemented in a prototype software frame- work called COMPAANPRO . The approach has been applied and validated successfully on a real ...
4. RESULTS Most of the steps in our approach , presented in Section 2 and Section 3 , have been implemented in a prototype software frame- work called COMPAANPRO . The approach has been applied and validated successfully on a real ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires