CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 90.
90. lappuse
... application is specified by the application developer does not match the way multi - processor ar- chitectures operate . The applications are typically specified using Permission to make digital or hard copies of all or part of this ...
... application is specified by the application developer does not match the way multi - processor ar- chitectures operate . The applications are typically specified using Permission to make digital or hard copies of all or part of this ...
91. lappuse
... application . There- fore , the techniques we present in this paper extend significantly the class of applications ... Application . application consists of three function calls ' F1 , F2 and F3 . These function calls execute tasks that ...
... application . There- fore , the techniques we present in this paper extend significantly the class of applications ... Application . application consists of three function calls ' F1 , F2 and F3 . These function calls execute tasks that ...
183. lappuse
... application model , each process records its actions in order to generate its own trace of application events which is nec- essary for driving an architecture model . There are three types of application events in two groups : execute ...
... application model , each process records its actions in order to generate its own trace of application events which is nec- essary for driving an architecture model . There are three types of application events in two groups : execute ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires