CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 76.
153. lappuse
... Analysis Power analysis at the early stage of design is also an important component of SEAS . At this early stage , the typical way to estimate power consumption uses spreadsheets based on conventional or empirical power formulas ...
... Analysis Power analysis at the early stage of design is also an important component of SEAS . At this early stage , the typical way to estimate power consumption uses spreadsheets based on conventional or empirical power formulas ...
201. lappuse
... analysis tech- nique to estimate CRPD . Our technique performs path anal- ysis of both the preempted and the preempting tasks . Fur- thermore , we improve the accuracy of the analysis by esti- mating the possible states of the entire ...
... analysis tech- nique to estimate CRPD . Our technique performs path anal- ysis of both the preempted and the preempting tasks . Fur- thermore , we improve the accuracy of the analysis by esti- mating the possible states of the entire ...
218. lappuse
... analysis optimization . ( The GC controlled scheme is also used . ) 100 % 90 % + 80 % 70 % 60 % 50 % 40 % 30 % 20 % 10 % 0 % calculator chess Dynamic Live Last Used Garbage Overhead emailviewer manyballs Figure 11 : Data Cache energy of ...
... analysis optimization . ( The GC controlled scheme is also used . ) 100 % 90 % + 80 % 70 % 60 % 50 % 40 % 30 % 20 % 10 % 0 % calculator chess Dynamic Live Last Used Garbage Overhead emailviewer manyballs Figure 11 : Data Cache energy of ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires