CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 90.
14. lappuse
... Algorithm 1 describes how Static Instruction Decoder of Figure 1 works . This algorithm accepts the target program binary and the instruction specification as inputs and generates a source file containing decoded instructions as output ...
... Algorithm 1 describes how Static Instruction Decoder of Figure 1 works . This algorithm accepts the target program binary and the instruction specification as inputs and generates a source file containing decoded instructions as output ...
130. lappuse
... Algorithm 5. The Nash equilibrium for the game is calculated using Algorithm 2 to determine the optimal binding of the operations to the modules and also obtain the power optimal schedule . The register binding task determines the ...
... Algorithm 5. The Nash equilibrium for the game is calculated using Algorithm 2 to determine the optimal binding of the operations to the modules and also obtain the power optimal schedule . The register binding task determines the ...
148. lappuse
Algorithm 3.1 An Standard Approach ( STDu ) Input : DFG G = ( V , E , d , t ) , iteration period constraint P and code size constraint M. Output : The minimum ... algorithm . The code size generated by the IDOMe algorithm is 90 148.
Algorithm 3.1 An Standard Approach ( STDu ) Input : DFG G = ( V , E , d , t ) , iteration period constraint P and code size constraint M. Output : The minimum ... algorithm . The code size generated by the IDOMe algorithm is 90 148.
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires