CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 51.
8. lappuse
... achieve higher accuracy of the performance estimation . However , current approaches do not cope with the requirements introduced by the system level design of full - fledged on - chip net- works . In order to apply analytical ...
... achieve higher accuracy of the performance estimation . However , current approaches do not cope with the requirements introduced by the system level design of full - fledged on - chip net- works . In order to apply analytical ...
144. lappuse
... achieve high - quality designs . This paper presents an Integrated Framework for Design Optimization and Space Minimization ( IDOM ) towards finding the minimum configuration satisfying timing and code size constraints . We show an ...
... achieve high - quality designs . This paper presents an Integrated Framework for Design Optimization and Space Minimization ( IDOM ) towards finding the minimum configuration satisfying timing and code size constraints . We show an ...
189. lappuse
... achieve minimum latency , packets are always forwarded . Error correction is performed , the underlying assumption is that all errors can be corrected by the code used . This mode is well suited for applications that can tolerate rare ...
... achieve minimum latency , packets are always forwarded . Error correction is performed , the underlying assumption is that all errors can be corrected by the code used . This mode is well suited for applications that can tolerate rare ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires