CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 36.
22. lappuse
... abstraction models Extending the SystemC Synthesis Subset by Object - Oriented Features. Models Specification model ... abstraction to lower level abstraction are inserted to bridge the PEs and the bus interfaces . Similar to the bus ...
... abstraction models Extending the SystemC Synthesis Subset by Object - Oriented Features. Models Specification model ... abstraction to lower level abstraction are inserted to bridge the PEs and the bus interfaces . Similar to the bus ...
52. lappuse
... abstraction for application users to interact with sensor networks . Just as in data - centric routing and storage where physical nodes are less important than the data itself , state - centric abstraction introduces " states " as a ...
... abstraction for application users to interact with sensor networks . Just as in data - centric routing and storage where physical nodes are less important than the data itself , state - centric abstraction introduces " states " as a ...
176. lappuse
... abstraction level , it provides formal design transformation methods for a transparent refinement process of the specification model into an implementation model that is optimized for synthesis . A transformation may be semantic ...
... abstraction level , it provides formal design transformation methods for a transparent refinement process of the specification model into an implementation model that is optimized for synthesis . A transformation may be semantic ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires