CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 61.
xi. lappuse
... University of Bologna , Italy Joe Buck , Synopsys , USA Sujit Dey , University of California , San Diego , USA Rolf Ernst , Technical University of Braunschweig , Germany Daniel Gajski , University of California , Irvine , USA Cathy ...
... University of Bologna , Italy Joe Buck , Synopsys , USA Sujit Dey , University of California , San Diego , USA Rolf Ernst , Technical University of Braunschweig , Germany Daniel Gajski , University of California , Irvine , USA Cathy ...
xiii. lappuse
... University of Technology , The Netherlands Tetsuya Aoyama , NEC , Japan Baris Arslan , University of California , San Diego , USA Isabelle Augé - Blum , INSA Lyon , France Rodolfo Azevedo , University of Campinas , Brazil Jean ...
... University of Technology , The Netherlands Tetsuya Aoyama , NEC , Japan Baris Arslan , University of California , San Diego , USA Isabelle Augé - Blum , INSA Lyon , France Rodolfo Azevedo , University of Campinas , Brazil Jean ...
xiv. lappuse
... University of Castilla - La Mancha , Spain José Manuel Moya , University of Madrid , Spain Akira Mukaiyama , NEC , Japan Shoubhik Mukhopadhyay , University of California , San Diego , USA Richard Murphy , University of Notre Dame , USA ...
... University of Castilla - La Mancha , Spain José Manuel Moya , University of Madrid , Spain Akira Mukaiyama , NEC , Japan Shoubhik Mukhopadhyay , University of California , San Diego , USA Richard Murphy , University of Notre Dame , USA ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires