CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 83.
5. lappuse
... Table 1 . Also , the priorities of the tasks are assigned as shown in Table 1 . We assume that the period of a task equals to its deadline . The tick size is set to 10 ms for both eCOS and uCOS . Even though the OS modeling technique is ...
... Table 1 . Also , the priorities of the tasks are assigned as shown in Table 1 . We assume that the period of a task equals to its deadline . The tick size is set to 10 ms for both eCOS and uCOS . Even though the OS modeling technique is ...
113. lappuse
Table 4 : Execution time ( seconds ) of ROCM , ROCM - 32 , and CD - ROCM - 32 for IP routing table reduction , and speedup of CD- ROCM - 32 versus ROCM executing on a 75MHz ARM7 . Table 5 : Execution time ( seconds ) of ROCM , ROCM ...
Table 4 : Execution time ( seconds ) of ROCM , ROCM - 32 , and CD - ROCM - 32 for IP routing table reduction , and speedup of CD- ROCM - 32 versus ROCM executing on a 75MHz ARM7 . Table 5 : Execution time ( seconds ) of ROCM , ROCM ...
117. lappuse
... Table 2 : Schedule Tree Construction in QDS schedule_tree ( H , G , S , w , μ ) H : set of EQSS schedules ; G : group of concurrently enabled transitions ; S : set of RTPN ; w : global real - time constraints ; // periods , deadlines ...
... Table 2 : Schedule Tree Construction in QDS schedule_tree ( H , G , S , w , μ ) H : set of EQSS schedules ; G : group of concurrently enabled transitions ; S : set of RTPN ; w : global real - time constraints ; // periods , deadlines ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires