CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 91.
145. lappuse
... Section 5 , we present the experimental results on a set of DSP benchmarks . Finally , concluding remarks are provided in Section 6 . 2. OPTIMIZATION TECHNIQUES AND DE- SIGN SPACE MINIMIZATION In this section , we present the the ...
... Section 5 , we present the experimental results on a set of DSP benchmarks . Finally , concluding remarks are provided in Section 6 . 2. OPTIMIZATION TECHNIQUES AND DE- SIGN SPACE MINIMIZATION In this section , we present the the ...
169. lappuse
... Section 2. In Section 3 , we describe the subset of eBlocks that we have addressed so far , known as Boolean eBlocks . Section 4 highlights numerous challenges and solutions in designing Boolean eBlocks . Section 5 describes several ...
... Section 2. In Section 3 , we describe the subset of eBlocks that we have addressed so far , known as Boolean eBlocks . Section 4 highlights numerous challenges and solutions in designing Boolean eBlocks . Section 5 describes several ...
226. lappuse
... Section 2 describes the methodology employed in our work and the parameters of the simulation environment . The synthetic network traffic trace is de- scribed as well . Section 3 presents various results of performance evaluation with ...
... Section 2 describes the methodology employed in our work and the parameters of the simulation environment . The synthetic network traffic trace is de- scribed as well . Section 3 presents various results of performance evaluation with ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires