CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 23.
5. lappuse
... RTOS is actually executed on the ISS . 6. EXPERIMENTS In this section , we show some preliminary experimental results on the performance improvement and on the accuracy . We consider a real - life multimedia application , a video phone ...
... RTOS is actually executed on the ISS . 6. EXPERIMENTS In this section , we show some preliminary experimental results on the performance improvement and on the accuracy . We consider a real - life multimedia application , a video phone ...
33. lappuse
... RTOS Busdriver read y protocol write Bus driver Z { / * OS management * / void init ( ) ; void start ( int sched_alg ) ; / * Task management * / Task task_create ( const char * name , int type , sim_time period ) ; void task_terminate ...
... RTOS Busdriver read y protocol write Bus driver Z { / * OS management * / void init ( ) ; void start ( int sched_alg ) ; / * Task management * / Task task_create ( const char * name , int type , sim_time period ) ; void task_terminate ...
34. lappuse
... RTOS Model Instantiation As the first step of the scheduling refinement , a RTOS model implementing interface RTOS is selected from the RTOS library and a run time environment which coordi- nates the interaction between the RTOS model ...
... RTOS Model Instantiation As the first step of the scheduling refinement , a RTOS model implementing interface RTOS is selected from the RTOS library and a run time environment which coordi- nates the interaction between the RTOS model ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires