CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 88.
35. lappuse
... Figure 5 : Task modeling Figure 7 shows the synchronization refinement for our ex- ample : the wait statement inside channel C1 in the input model ( line 10 in Figure 7 ( a ) ) is refined into three lines of code in the output model ...
... Figure 5 : Task modeling Figure 7 shows the synchronization refinement for our ex- ample : the wait statement inside channel C1 in the input model ( line 10 in Figure 7 ( a ) ) is refined into three lines of code in the output model ...
89. lappuse
... Figure 10 , the average run time for step 1 was 11.7s ( 60 tasks ) , 40.1s ( 75 tasks ) , 73.2s ( 90 tasks ) , and 150s ( 120 tasks ) . The execution time for step 2 is presented in more detail in Figure 12 and Figure 13. Figure 12 ...
... Figure 10 , the average run time for step 1 was 11.7s ( 60 tasks ) , 40.1s ( 75 tasks ) , 73.2s ( 90 tasks ) , and 150s ( 120 tasks ) . The execution time for step 2 is presented in more detail in Figure 12 and Figure 13. Figure 12 ...
186. lappuse
... Figure 4 : M - JPEG * encoder application model . VOP ) , an SRAM and a DRAM . For these architecture components , realistic latency values from [ 7 ] have been used to calculate their processing capacities : cp and Cm . Similarly , for ...
... Figure 4 : M - JPEG * encoder application model . VOP ) , an SRAM and a DRAM . For these architecture components , realistic latency values from [ 7 ] have been used to calculate their processing capacities : cp and Cm . Similarly , for ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires