Architecture Exploration for Embedded Processors with LISASpringer Science & Business Media, 2013. gada 29. jūn. - 230 lappuses Already today more than 90% of all programmable processors are employed in embedded systems. This number is actually not surprising, contemplating that in a typical home you might find one or two PCs equipped with high of embedded systems, performance standard processors, but probably dozens including electronic entertainment, household, and telecom devices, each of them equipped with one or more embedded processors. Moreover, the elec tronic components of upper-class cars incorporate easily over one hundred pro cessors. Hence, efficient embedded processor design is certainly an area worth looking at. The question arises why programmable processors are so popular in embed ded system design. The answer lies in the fact that they help to narrow the gap between chip capacity and designer productivity. Embedded processors cores are nothing but one step further towards improved design reuse, just along the lines of standard cells in logic synthesis and macrocells in RTL synthesis in earlier times of IC design. Additionally, programmable processors permit to migrate functionality from hardware to software, resulting in an even improved reuse factor as well as greatly increased flexibility. |
No grāmatas satura
1.–5. rezultāts no 92.
vi. lappuse
... models in the LISA language . It supports a profiling - based , stepwise refinement of processor models down to cycle - accurate and even RTL synthesis models . Moreover , it elegantly avoids model inconsistencies otherwise omnipresent ...
... models in the LISA language . It supports a profiling - based , stepwise refinement of processor models down to cycle - accurate and even RTL synthesis models . Moreover , it elegantly avoids model inconsistencies otherwise omnipresent ...
9. lappuse
... LISA [ 25 ] . 3 . Organization of this Book This book is organized as ... LISA language underlying this work . These processor models are required to address ... model resulting from the architecture exploration phase can be reused to ...
... LISA [ 25 ] . 3 . Organization of this Book This book is organized as ... LISA language underlying this work . These processor models are required to address ... model resulting from the architecture exploration phase can be reused to ...
14. lappuse
... model . Obviously , the implementation model comprises micro - architectural information that is not needed for the software simulator . However , it is diffi- cult , in most cases even impossible for the software designer to abstract ...
... model . Obviously , the implementation model comprises micro - architectural information that is not needed for the software simulator . However , it is diffi- cult , in most cases even impossible for the software designer to abstract ...
16. lappuse
... model control - flow and inter - instruction dependencies . By this , pipelines can be modeled as well as mechanisms ... LISA incorporates ideas similar to nML . In fact , large parts of the LISA language are following the pattern of nML ...
... model control - flow and inter - instruction dependencies . By this , pipelines can be modeled as well as mechanisms ... LISA incorporates ideas similar to nML . In fact , large parts of the LISA language are following the pattern of nML ...
17. lappuse
... model with the information if they are registers , memories , or transitory storages , a type specifier , and ( in case they are array structure ) the width . nML : let wordsize = 16 , type word = int ( wordsize ) , reg R [ 8 , word ] In ...
... model with the information if they are registers , memories , or transitory storages , a type specifier , and ( in case they are array structure ) the width . nML : let wordsize = 16 , type word = int ( wordsize ) , reg R [ 8 , word ] In ...
Saturs
11 | |
PROCESSOR MODELS FOR ASIP DESIGN | 31 |
2 | 42 |
ARCHITECTURE EXPLORATION | 57 |
ARCHITECTURE IMPLEMENTATION | 79 |
SOFTWARE TOOLS FOR APPLICATION DESIGN | 101 |
SYSTEM INTEGRATION AND VERIFICATION | 129 |
SUMMARY AND OUTLOOK | 143 |
Appendices | 149 |
List of Figures | 203 |
Bibliography | 210 |
46 | 214 |
About the Authors 224 | 225 |
Citi izdevumi - Skatīt visu
Architecture Exploration for Embedded Processors with LISA Andreas Hoffmann,Heinrich Meyr,Rainer Leupers Ierobežota priekšskatīšana - 2002 |
Architecture Exploration for Embedded Processors with LISA Andreas Hoffmann,Heinrich Meyr,Rainer Leupers Priekšskatījums nav pieejams - 2010 |
Architecture Exploration for Embedded Processors with Lisa Andreas Hoffmann,Heinrich Meyr,Rainer Leupers Priekšskatījums nav pieejams - 2014 |
Bieži izmantoti vārdi un frāzes
abstraction activation ADPCM adreg Advanced Risc Machines algorithm architecture exploration ARM7 ASIP assembler base_reg BEHAVIOR binary branch instruction chapter combinatoric compiled simulation CORDIC CPSR data-path debugger frontend DECLARE description language dest dynamic scheduling Entity execution fetch Figure functional units graphical debugger GROUP hardware hardware description language HDL code HDL model ICORE architecture instantiation instruction pipeline instruction word instruction-set interpretive simulation keyword LABEL linker LISA description LISA language LISA model LISA operations LISA processor design LISA processor models machine descriptions memory model in LISA Opcode phase pipeline control pipeline registers pipeline stages power consumption processor design platform processor resources R_mode regd retargetable save_register current_pos++ signal Simulation compilation simulation speed simulation technique software development tools software simulator specification src2 stall static scheduling Status Registers SYNTAX synthesis system simulation SystemC target architecture Texas Instruments Verilog VHDL VLIW