Architecture Exploration for Embedded Processors with LISASpringer Science & Business Media, 2013. gada 29. jūn. - 230 lappuses Already today more than 90% of all programmable processors are employed in embedded systems. This number is actually not surprising, contemplating that in a typical home you might find one or two PCs equipped with high of embedded systems, performance standard processors, but probably dozens including electronic entertainment, household, and telecom devices, each of them equipped with one or more embedded processors. Moreover, the elec tronic components of upper-class cars incorporate easily over one hundred pro cessors. Hence, efficient embedded processor design is certainly an area worth looking at. The question arises why programmable processors are so popular in embed ded system design. The answer lies in the fact that they help to narrow the gap between chip capacity and designer productivity. Embedded processors cores are nothing but one step further towards improved design reuse, just along the lines of standard cells in logic synthesis and macrocells in RTL synthesis in earlier times of IC design. Additionally, programmable processors permit to migrate functionality from hardware to software, resulting in an even improved reuse factor as well as greatly increased flexibility. |
No grāmatas satura
1.–5. rezultāts no 48.
vii. lappuse
... model of the target architecture is supported in the latest version of LISA . By this , the complete processor ... micro - controllers ( Cs ) and special purpose architectures . All in all , more than 40 man - years of effort by PhD ...
... model of the target architecture is supported in the latest version of LISA . By this , the complete processor ... micro - controllers ( Cs ) and special purpose architectures . All in all , more than 40 man - years of effort by PhD ...
8. lappuse
... architecture exploration phase to map the target application most efficiently to an instruction - set and a micro - architecture , the generation of a synthesizable implementation model , the generation of application software ...
... architecture exploration phase to map the target application most efficiently to an instruction - set and a micro - architecture , the generation of a synthesizable implementation model , the generation of application software ...
9. lappuse
... model , and system integration and verification . Besides , the capability of the language to abstract from the processor architecture on various levels in the domain of architecture ... micro- architecture needs to be specified in a hardware ...
... model , and system integration and verification . Besides , the capability of the language to abstract from the processor architecture on various levels in the domain of architecture ... micro- architecture needs to be specified in a hardware ...
10. lappuse
... architecture design , chapter 7 focuses on software development tools required to program the ... micro - controller architectures will show the quality of the tools by ... model of the ARM7 μC architecture , and some details on the ICORE ...
... architecture design , chapter 7 focuses on software development tools required to program the ... micro - controller architectures will show the quality of the tools by ... model of the ARM7 μC architecture , and some details on the ICORE ...
12. lappuse
Andreas Hoffmann, Heinrich Meyr, Rainer Leupers. Architecture Exploration ⚫ instruction - set design • micro - architecture • HW / SW partitioning Architecture Implementation realization of HDL model ( VHDL , Verilog ) • synthesis ...
Andreas Hoffmann, Heinrich Meyr, Rainer Leupers. Architecture Exploration ⚫ instruction - set design • micro - architecture • HW / SW partitioning Architecture Implementation realization of HDL model ( VHDL , Verilog ) • synthesis ...
Saturs
11 | |
PROCESSOR MODELS FOR ASIP DESIGN | 31 |
2 | 42 |
ARCHITECTURE EXPLORATION | 57 |
ARCHITECTURE IMPLEMENTATION | 79 |
SOFTWARE TOOLS FOR APPLICATION DESIGN | 101 |
SYSTEM INTEGRATION AND VERIFICATION | 129 |
SUMMARY AND OUTLOOK | 143 |
Appendices | 149 |
List of Figures | 203 |
Bibliography | 210 |
46 | 214 |
About the Authors 224 | 225 |
Citi izdevumi - Skatīt visu
Architecture Exploration for Embedded Processors with LISA Andreas Hoffmann,Heinrich Meyr,Rainer Leupers Ierobežota priekšskatīšana - 2002 |
Architecture Exploration for Embedded Processors with LISA Andreas Hoffmann,Heinrich Meyr,Rainer Leupers Priekšskatījums nav pieejams - 2010 |
Architecture Exploration for Embedded Processors with Lisa Andreas Hoffmann,Heinrich Meyr,Rainer Leupers Priekšskatījums nav pieejams - 2014 |
Bieži izmantoti vārdi un frāzes
abstraction activation ADPCM adreg Advanced Risc Machines algorithm architecture exploration ARM7 ASIP assembler base_reg BEHAVIOR binary branch instruction chapter combinatoric compiled simulation CORDIC CPSR data-path debugger frontend DECLARE description language dest dynamic scheduling Entity execution fetch Figure functional units graphical debugger GROUP hardware hardware description language HDL code HDL model ICORE architecture instantiation instruction pipeline instruction word instruction-set interpretive simulation keyword LABEL linker LISA description LISA language LISA model LISA operations LISA processor design LISA processor models machine descriptions memory model in LISA Opcode phase pipeline control pipeline registers pipeline stages power consumption processor design platform processor resources R_mode regd retargetable save_register current_pos++ signal Simulation compilation simulation speed simulation technique software development tools software simulator specification src2 stall static scheduling Status Registers SYNTAX synthesis system simulation SystemC target architecture Texas Instruments Verilog VHDL VLIW