Functional Verification of Programmable Embedded Architectures: A Top-Down ApproachSpringer Science & Business Media, 2005. gada 6. dec. - 180 lappuses It is widely acknowledged that the cost of validation and testing comprises a s- nificant percentage of the overall development costs for electronic systems today, and is expected to escalate sharply in the future. Many studies have shown that up to 70% of the design development time and resources are spent on functional verification. Functional errors manifest themselves very early in the design flow, and unless they are detected up front, they can result in severe consequence- both financially and from a safety viewpoint. Indeed, several recent instances of high-profile functional errors (e. g. , the Pentium FDIV bug) have resulted in - creased attention paid to verifying the functional correctness of designs. Recent efforts have proposed augmenting the traditional RTL simulation-based validation methodology with formal techniques in an attempt to uncover hard-to-find c- ner cases, with the goal of trying to reach RTL functional verification closure. However, what is often not highlighted is the fact that in spite of the tremendous time and effort put into such efforts at the RTL and lower levels of abstraction, the complexity of contemporary embedded systems makes it difficult to guarantee functional correctness at the system level under all possible operational scenarios. The problem is exacerbated in current System-on-Chip (SOC) design meth- ologies that employ Intellectual Property (IP) blocks composed of processor cores, coprocessors, and memory subsystems. Functional verification becomes one of the major bottlenecks in the design of such systems. |
No grāmatas satura
1.–5. rezultāts no 53.
. lappuse
... Structural ADLs 2.1.3 Mixed ADLS 2.1.4 II Architecture Specification 2 Architecture Specification Architecture Description Languages 13 15 16 18 19 19 2.3.1 2.3.2 Partial ADLS 2.2 ADLs and Other Specification Languages 2.3 Specification ...
... Structural ADLs 2.1.3 Mixed ADLS 2.1.4 II Architecture Specification 2 Architecture Specification Architecture Description Languages 13 15 16 18 19 19 2.3.1 2.3.2 Partial ADLS 2.2 ADLs and Other Specification Languages 2.3 Specification ...
. lappuse
... Structure of a Generic Processor 4.2.2 Behavior of a Generic Processor 4.2.3 4.2.4 Generic Controller 4.2.5 Structure of a Generic Memory Subsystem · Interrupts and Exceptions Reference Model Generation 4.4 Related Work · 4.5 Chapter ...
... Structure of a Generic Processor 4.2.2 Behavior of a Generic Processor 4.2.3 4.2.4 Generic Controller 4.2.5 Structure of a Generic Memory Subsystem · Interrupts and Exceptions Reference Model Generation 4.4 Related Work · 4.5 Chapter ...
. lappuse
... Structural ADLs . 127 A.2 Behavioral ADLs 130 • A.3 Mixed ADLs 134 E.1 A.4 Partial ADLs B Specification of DLX Processor C Interrupts & Exceptions in ADL D Validation of DLX Specification E Design Space Exploration Simulator Generation ...
... Structural ADLs . 127 A.2 Behavioral ADLs 130 • A.3 Mixed ADLs 134 E.1 A.4 Partial ADLs B Specification of DLX Processor C Interrupts & Exceptions in ADL D Validation of DLX Specification E Design Space Exploration Simulator Generation ...
. lappuse
... structure using EXPRESSION ADL 2.7 Specification of the processor behavior using EXPRESSION ADL 2.8 Coprocessor specification using EXPRESSION ADL 2.9 Memory subsystem specification using EXPRESSION ADL 3.1 Validation of pipeline ...
... structure using EXPRESSION ADL 2.7 Specification of the processor behavior using EXPRESSION ADL 2.8 Coprocessor specification using EXPRESSION ADL 2.9 Memory subsystem specification using EXPRESSION ADL 3.1 Validation of pipeline ...
5. lappuse
... structural RTL code in each design , indicating a roughly constant density [ 11 ] . Simple extrapolation indicates that unless a radically new approach is em- ployed , we can expect to see 20-30K bugs designed into the next generation ...
... structural RTL code in each design , indicating a roughly constant density [ 11 ] . Simple extrapolation indicates that unless a radically new approach is em- ployed , we can expect to see 20-30K bugs designed into the next generation ...
Saturs
1 | 12 |
Architecture Specification | 20 |
Validation of Specification | 29 |
Architecture Specification | 49 |
16 | 55 |
Executable Model Generation | 64 |
Interrupts and Exceptions | 75 |
Design Validation | 84 |
Conclusions | 121 |
B Specification of DLX Processor 141 | 140 |
Interrupts Exceptions in ADL | 147 |
E Design Space Exploration | 155 |
References | 167 |
73 | 173 |
Index | 179 |
Functional Test Generation | 95 |
Citi izdevumi - Skatīt visu
Functional Verification of Programmable Embedded Architectures: A Top-Down ... Prabhat Mishra,Nikil D. Dutt Ierobežota priekšskatīšana - 2005 |
Functional Verification of Programmable Embedded Architectures: A Top-Down ... Prabhat Mishra,Nikil D. Dutt Priekšskatījums nav pieejams - 2014 |
Bieži izmantoti vārdi un frāzes
ADL description ADL specification Algorithm applied Architecture Specification cache capture code coverage compiler components computation cond configuration coprocessor data-transfer paths decode unit describes design space exploration detecting faults DLX architecture DLX processor embedded systems endfor endif Equation equivalence checking example execution path execution unit EXPRESSION ADL FADD false pipeline fault model fetch unit framework FSM model functional abstraction functional coverage functional units graph model implementation in-order execution input instruction register instruction-set interrupt IRij ISDL language LATCHES mapping memory subsystem MIMOLA model checking node opcode operands operation execution out-of-order out-of-order execution output performance pipeline and data-transfer pipeline execution pipeline path pipeline stages pipelined processor presents processor pipeline programmable architectures reference model register file register read/write retargetable compilation RISC shown in Figure Specman Elite SRAM SRC2 stalled storage structure sub-functions superscalar supported symbolic simulation test programs TestProgramList tion verify VHDL VLIW WriteBack