Functional Verification of Programmable Embedded Architectures: A Top-Down Approach

Pirmais vāks
Springer Science & Business Media, 2005. gada 6. dec. - 180 lappuses
It is widely acknowledged that the cost of validation and testing comprises a s- nificant percentage of the overall development costs for electronic systems today, and is expected to escalate sharply in the future. Many studies have shown that up to 70% of the design development time and resources are spent on functional verification. Functional errors manifest themselves very early in the design flow, and unless they are detected up front, they can result in severe consequence- both financially and from a safety viewpoint. Indeed, several recent instances of high-profile functional errors (e. g. , the Pentium FDIV bug) have resulted in - creased attention paid to verifying the functional correctness of designs. Recent efforts have proposed augmenting the traditional RTL simulation-based validation methodology with formal techniques in an attempt to uncover hard-to-find c- ner cases, with the goal of trying to reach RTL functional verification closure. However, what is often not highlighted is the fact that in spite of the tremendous time and effort put into such efforts at the RTL and lower levels of abstraction, the complexity of contemporary embedded systems makes it difficult to guarantee functional correctness at the system level under all possible operational scenarios. The problem is exacerbated in current System-on-Chip (SOC) design meth- ologies that employ Intellectual Property (IP) blocks composed of processor cores, coprocessors, and memory subsystems. Functional verification becomes one of the major bottlenecks in the design of such systems.

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List of Figures
4
Architecture Specification
15
tures
16
Validation of Specification
29
E 8
58
Executable Model Generation 65
64
Modeling of RenameRegister function using subfunctions
72
Design Validation
83
A fragment of the DLX architecture
100
Validation of the Implementation
114
Conclusions
121
B Specification of DLX Processor 141
147
Specification of division_by_zero exception
148
E Design Space Exploration
155
Cycle counts for the memory configurations
162
References
167

Test vectors for validation of an AND gate
85
Functional Test Generation
95
Index
179
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