Functional Verification of Programmable Embedded Architectures: A Top-Down Approach
It is widely acknowledged that the cost of validation and testing comprises a s- nificant percentage of the overall development costs for electronic systems today, and is expected to escalate sharply in the future. Many studies have shown that up to 70% of the design development time and resources are spent on functional verification. Functional errors manifest themselves very early in the design flow, and unless they are detected up front, they can result in severe consequence- both financially and from a safety viewpoint. Indeed, several recent instances of high-profile functional errors (e. g. , the Pentium FDIV bug) have resulted in - creased attention paid to verifying the functional correctness of designs. Recent efforts have proposed augmenting the traditional RTL simulation-based validation methodology with formal techniques in an attempt to uncover hard-to-find c- ner cases, with the goal of trying to reach RTL functional verification closure. However, what is often not highlighted is the fact that in spite of the tremendous time and effort put into such efforts at the RTL and lower levels of abstraction, the complexity of contemporary embedded systems makes it difficult to guarantee functional correctness at the system level under all possible operational scenarios. The problem is exacerbated in current System-on-Chip (SOC) design meth- ologies that employ Intellectual Property (IP) blocks composed of processor cores, coprocessors, and memory subsystems. Functional verification becomes one of the major bottlenecks in the design of such systems.
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Validation of Speciﬁcation
Executable Model Generation 65
Modeling of RenameRegister function using subfunctions
A fragment of the DLX architecture
Validation of the Implementation
B Speciﬁcation of DLX Processor 141
Speciﬁcation of division_by_zero exception
E Design Space Exploration
Cycle counts for the memory conﬁgurations
Test vectors for validation of an AND gate
Functional Test Generation
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Functional Verification of Programmable Embedded Architectures: A Top-Down ...
Prabhat Mishra,Nikil D. Dutt
Ierobežota priekšskatīšana - 2005
ADL speciﬁcation Algorithm applied Architecture Description Language Architecture Speciﬁcation behavior bugs cache capture compiler components computation conﬁguration coprocessor data-transfer paths deﬁned deﬁnition describes DEST DLX architecture DLX processor edges embedded systems endfor Equation equivalence checking example execution path execution unit EXPRESSION ADL false pipeline fault model ﬁelds ﬁrst ﬂow ﬂushed framework functional abstraction functional coverage functional units golden reference model graph model implementation in-order execution input instruction register instruction-set ISDL LATCHES mapping memory subsystem MIMOLA model checking modiﬁed node opcode operands out-of-order out-of-order execution output performance pipeline and data-transfer pipeline path pipeline stages pipelined processor processor pipeline programmable architectures property checking register ﬁle retargetable compilation ripple-carry adder RISC satisﬁes shown in Figure speciﬁcation language Specman Elite SRAM SRC2 srcl stalled storage structure sub-functions superscalar symbolic simulation test programs TestProgramList tion top-down validation methodology verify VHDL VLIW WriteBack