Low-Power Deep Sub-Micron CMOS Logic: Sub-threshold Current ReductionSpringer Science & Business Media, 2004 - 154 lappuses The strong interaction between the demand for increasing chip functionality and data-processing speeds, and technological trends in the integrated circuit industry, like e.g. shrinking device geometry, growing chip area and increased transistor switching speeds, cause a huge increase in power dissipation for deep sub-micron digital CMOS circuits. Low-Power Deep Sub-micron CMOS Logic, Sub-threshold Current Reduction classifies all power dissipation sources in digital CMOS circuits and provides for a systematic approach of power reduction techniques. A clear distinction has been made between power dissipated to perform a calculation in a certain time frame, i.e. functional power dissipation, and power dissipated even when a circuit is idle, i.e. parasitical power dissipation. The threshold voltage level forms an important link between the functional and the parasitical power dissipation. Since for high data-processing speeds the threshold voltage needs to be low, whereas for low sub-threshold leakage currents it needs to be high. The latter is extremely important for battery operated circuits in standby modes. Therefore, a separate classification of sub-threshold current reduction techniques is presented showing existing and new circuit topologies. Low-Power Deep Sub-micron CMOS Logic, Sub-threshold Current Reduction is a valuable book for researchers, designers as well as students in the field of low-power digital design. Power dissipation is discussed from a fundamental, quantum mechanical and a practical point of view. Theory is accompanied with practical circuit implementations and measurement results. |
Saturs
INTRODUCTION | 1 |
POWER VERSUS ENERGY | 5 |
POWER DISSIPATION IN DIGITAL CMOS CIRCUITS | 11 |
REDUCTION OF FUNCTIONAL POWER DISSIPATION | 53 |
REDUCTION OF PARASITICAL POWER DISSIPATION | 77 |
WEAKINVERSION CURRENT REDUCTION | 93 |
EFFECTIVENESS OF WEAKINVERSION CURRENT REDUCTION | 105 |
TRIPLES CIRCUIT DESIGNS | 121 |
CONCLUSIONS | 139 |
SUMMARY | 141 |
Citi izdevumi - Skatīt visu
Low-Power Deep Sub-Micron CMOS Logic: Sub-threshold Current Reduction P. van der Meer,A. van Staveren,Arthur H.M. van Roermund Ierobežota priekšskatīšana - 2012 |
Low-Power Deep Sub-Micron CMOS Logic P. Van Der Meer,A. Van Staveren,Arthur H M Van Roermund Priekšskatījums nav pieejams - 2005 |
Low-Power Deep Sub-Micron CMOS Logic: Sub-threshold Current Reduction P. van der Meer,A. van Staveren,Arthur H.M. van Roermund Priekšskatījums nav pieejams - 2012 |
Bieži izmantoti vārdi un frāzes
active periods applications average break-even standby channel leakage current charge circuit node clock frequency clock period CMOS CMOS circuits CMOS technology decrease discussed in section doping concentration drain-source Dynamic voltage scaling effective threshold voltage Electron entropy equals equation figure functional power dissipation gate biasing gate insulator gate leakage currents gate oxide GIDL high threshold voltage IEEE increase latch leakage reduction leaky device logic gate mode switch MODEp NMOS transistor node transition-cycle activity overhead costs oxide thickness parameters parasitical power dissipation permittivity PMOS polysilicon power reduction power supply lines power switches propagation delay quasi-static reduction techniques reversibility factor reversible logic ring oscillator saturation current shallow trench isolation shift register short-circuit power dissipation signal source and drain speed performance standby mode standby periods substrate biasing supply voltage transitions Triple-S flip-flops tunneling current voltage scaling voltage swing weak-inversion current reduction weak-inversion leakage currents weak-inversion slope width