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engaged in training as well as pilot production. In 1991 more than 8,500 companies obtained some kind of technical service from ITRI and almost 40,000 people attended various seminars, workshops, or training courses. The staff generated about 350 patent applications, half outside of Taiwan. R&D activity is in

• Electronics

• Computers & Communications • Opto-electronics

• Measurement & Standards

Materials Chemicals

• Energy & Resources

• Machinery

• Aerospace

• Industrial Safety & Health • Industrial Pollution Control

The aerospace activity is new, begun in 1990 when ROC launched the National Initiative for Aerospace Industry Development.

The Computer & Communications Research Laboratories (CCL), where I spent most of my time, run by my host Mr. Wang, is also new, although it was spun off from an older Electronics Research and Services Organization whose job was to foster the IC and PC industries in Taiwan. (Acer is Taiwan's largest PC maker and offers a range of clone products including various high end machines.) Current IC production is just beginning to include the technology to make central processing units (CPUs). CCL and some local private firms are negotiating with MIPS for manufacturing MIPS's R4000 CPUs in Taiwan. There are also discussions between Hewlett-Packard (HP) and several local manufacturers about possible cooperation. CCL's focus is in three general areas.

(1) Workstation and peripherals, multimedia systems, and system software.

(2) Networking, both local area and

wide area networks (LAN and WAN), both to take advantage of the trend toward integrated services and data network (ISDN) and for more heterogeneous computing environments that are seen to be common in the 1990s.

(3) Consumer electronics, including improvements to analog devices using digital technology, high definition TV (HDTV), and related audio-visual products.

CCL has almost 1,000 staff members, including 40 with Ph.D. degrees, 440 with M.S. degrees, and 300 with B.S. degrees. The 1991 total budget was about $61M. Some specific projects that I saw include the following.

⚫A 40-MHz Sparc VME-based workstation, based on a RISC CPU and client/server architecture. A chipset for peripheral devices was also designed. A three-dimensional (3D) color graphics module, an interactive 3D graphics interface, etc. Quite a bit of this chip design was completed but it does not seem as if the actual packaging was completed. In any case the experience is described as the design of a super-mini. Based on this CCL is working on a file server and also, I was told, a multiprocessor and vector processor. I am somewhat skeptical about progress on these later projects, however, as my discussions with Wang did not suggest much interest in really high performance systems. There is substantial work on various open systems software tools.

• Research on Chinese character processing has been in progress since 1985 and includes printed Chinese character recognition, on-line character recognition, etc. CCL wants to expand its recognition work to

other languages, especially Japanese and English. There are projects on handwritten address recognition for the post office and form filling for numerous organizations. There is also machine translation research.

⚫ I was shown several demos of multimedia applications. These mostly involved building easy-to-use tools on top of commercial (U.S.) multimedia software.

There are projects to develop several new products, including at least two notebook PCs, a hand-held (palmtop) PC, an X-terminal, IC card, and a 900-MHz cordless radio frequency (RF) module. (Some of these may have already been completed.) These involve consortia with local companies. Given the state of current technology in these areas there is no reason to think that the projects will not be successful. A few of these projects involve liquid crystal display (LCD) technology, but I had no opportunity to learn about progress on this topic. One of the most interesting and practical of technology dissemination proj ects was an automated ticketing system for the Taipei railroad system. This has been installed and is in daily operation.

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an HD-camcorder and an HD-video cassette recorder. The HDTV projects are intended to revive what is seen as a declining consumer products industry, as well as to promote defense, medical, and other Taiwanese industries.

My general sense of work at CCL was that projects are not so different from those at some other Asian industrial research institutes. The research is applied and the emphasis is on excellent liaison with industry rather than excellent academic output. With so much emphasis on industry it is not surprising that staff turnover is high, with young scientists and engineers moving from CCL to industrial organizations with which they already have relationships. ITRI management is aware of the issue and is trying to address it by making the work and environment highly attractive. There is a great deal of enthusiasm and energy about working on interesting prototype projects by what appeared to me to be a relatively young staff. CCL seems to be engaged in exactly the kind of R&D that its charter and mission specify. The research activities are not too "far out," so it is possible for the staff to sense where they are going. I did not see (or was not shown) any really unusual directions. As in other laboratories in this part of the world, there is a heavy emphasis on building things and less emphasis on software. Equipment is good, but not as good as at first class research institutes in Japan or the United States; there were many PCs and fewer workstations than I expected. I did not see any work in algorithms or other aspects of computer science; work of this kind. would be more likely to occur at a university or the Academia Sinica. CCL did not appear to be much interested in supercomputing either. Also, surprisingly, my host was unaware of the Signal Processing and Communication

Systems Workshop that was to be held in the capital the day after my visit. Nevertheless, CCL seemed like an interesting place to work. Concerning cooperation with Western laboratories, Wang pointed out to me that because much of their work is tied to improving industrial activities, some projects might be off limits, but given that this could be off limits, but given that this could be handled, I think that there would be opportunities for Western researchers. On the other hand, young CCL staff could provide a welcome additional could provide a welcome additional pair of hands in Western laboratories as medium-term visitors.

NATIONAL CENTER FOR HIGH PERFORMANCE COMPUTING (NCHC)

I have described plans for NCHC in earlier reports and so will not repeat those here. My primary reason for a repeat visit was to see how the construction of the center was progressing and to learn if a decision had been made about a vendor. NCHC is being built just adjacent to the Hsinchu Science Park (see above), but surprisingly, my park administration hosts didn't know about it initially, and even later could not locate the construction activity amidst a great deal of other building projects except to say that it was "somewhere over there." However, I was assured by Prof. San-Cheng Chang, the NCHC Director, that construction is mostly on schedule and that a machine will be installed later this year.

At the moment the sole acceptable vendor is IBM, who proposed a fourvendor is IBM, who proposed a fourprocessor ES9000/A20 high end machine, each processor equipped with a vector unit. Permission has to be obtained from the Taiwanese Government to allow a sole source procurement and then NCHC staff will begin negotiations about details. The plan is to upgrade this in 1994, and IBM has proposed an SS1 for the

upgrade, with NCHC staff being allowed to make quarterly visits to the factory to check that progress on this machine is on schedule. Cray and NEC also made proposals but these did not qualify. Chang told me that Cray's proposal missed because the company made some errors in the paperwork they submitted. NEC's four-processor SX-3 did not run NCHC's seven benchmark programs as well as expected after tuning, and their upgrade, an SX-4, was only to be available in 1995. In fact, NCHC has repeatedly told me that having a strong Taiwan-based support team was an important part of their requirements, and IBM already has a very significant presence there.

While I was visiting NCHC's Taipei office I was introduced to Dr. Jean H. Su [E-mail: ajin@nchc.ntu.edu.tw]. Su is a former student of Prof. Steven Pruess, a well known numerical analyst at the University of New Mexico. During my travels in Asia I have met relatively few scientists with formal training in numerical mathematics and application to high performance computation. Su's presence at NCHC reaffirms my sense that this organization is going to focus on applications and provide professional support to their user community. Also while I was there I observed a course being taught by an American molecular biologist on the use of canned software for molecular modelling. This was tied in with a new visualization laboratory that had several SGI workstations and had just been opened.

INTELLIGENT SIGNAL PROCESSING AND COMMUNICATION SYSTEMS WORKSHOP (ISPACS'92)

This 1992 IEEE International Workshop, held from 19-21 March 1922 in Taipei, brought together about 150 people, including 35 from outside of Taiwan (half from Japan) and 45 students. The meeting organizers were

and

Prof. Lin-shan Lee

Prof. of Electrical Engineering Department of Computer Science

and Information Engineering National Taiwan University Taipei, Taiwan, ROC

Tel: +886-2-351-0231 x3212/3232

Dr. Tomonori Aoyama

Executive Manager, Transport

Processing Laboratory

NTT Transmission Systems
Laboratories

1-2356, Take

Yokosuka, Kanagawa 238-03, Japan
Tel: +81-468-59-3020
Fax: +81-468-59-3014

The motivation for this workshop was that the organizers (mostly coming from the hardware side of signal processing) felt that more computer science ideas need to be injected into the field of signal processing and that bringing members of both communities together would be a small step in that direction. Nevertheless, most of the participants were still heavily focused on hardware, so it was clear that a great deal more needs to be done to move these groups together.

Typically, this field has been heavily oriented toward digital signal processing (DSP) applications and especially techniques to increase the information content of signals by increasing the bit rate by using new physical medium, reducing the bits needed to be transmitted by compressing techniques, improvement of the output signal by echo cancellation, adaptive filters, signal transmission/equalization and finally speech, text, and character recognition/ synthesis, etc. (Signals can be speech, data, or video.) More interesting to me were the very different world views expressed by the two keynote speakers,

and

Prof. David G. Messerschmitt
Department of Electrical
Engineering & Computer Science
University of California
517 Cory Hall
Berkeley, CA 94720

Tel: (415) 642-1090

Fax: (415) 642-2739
E-mail: messer@janus.berkeley.edu

Dr. Takao Nishitani

Senior Manager, Terminal Systems
Research Laboratory
C&C Systems Research Laboratories
NEC Corporation
1-1, Miyazaka 4-chome
Miyamae-ku, Kawasaki
Kanagawa 216, Japan
Tel: +81-44-856-2118
Fax: +81-44-856-2232
E-mail: takao@tsl.cl.nec.co.jp

The titles of their talks speak volumes: Messerschmitt, "Telecommunications and Signal Processing: The Evolving Relationship"; Nishitani, "Hardware Relationship"; Nishitani, “Hardware Approaches to Signal Processing on Communication Systems."

Messerschmitt emphasized that telecommunications, signal processing, and computing are merging, even though he saw a polarization into wireless and optical transmission technologies with almost opposite bandwidth and reliability problems. He felt that in the ability problems. He felt that in the future a proliferation of services with smaller interest groups will mean that abstraction, complexity management, system design, and structured design methodologies will become increasingly important. He concluded that he was anxious to learn more about object oriented programming, which he felt will be a key to future developments. will be a key to future developments. Everyone agreed that his presentation Everyone agreed that his presentation was brilliant and exactly what was called for by the meeting organizers.

Nishitani emphasized that the community should concentrate not on abstraction but rather on building domain-specific digital signal processors and that this would enable DSPs to be developed that were small, required low power, and were low cost. (The speaker is a recognized expert in the field of programmable DSP and was responsible for the very early development of a single chip DSP for NEC.) Build it, try it, and learn from it might be his motto. Nishitani repeatedly described the possibilities for realizable hardware such as a domain specific video signal processor that can realize motion compensation in contrast to a mesh-parallel computer that he felt was too general and hence both too expensive and not powerful enough. Other examples included real-time computer graphics, high-resolution video, 3D video, a 128-module video signal processor for HDTV, and finally a video compression chipset that is available now, implementable because it was specific rather than general. Nishitani is also very interested in picture coding algorithms using wavelet transforms but gave no specific details of his work in this area.

To me, these papers were perfect metaphors for the different approaches to research as practiced in Japan and in the United States.

In addition to invited and presented talks, there was a full afternoon session devoted to posters. An English language Proceedings contains all the presented papers, not including the keynotes, unfortunately. There were several papers on the "hot" topic of digital communication. These centered on methods to code speech signals. Traditionally speech coders (the conversion of speech signals into digital data streams) have been judged on three major performance criteria: speech quality, rate (number of bits per second

necessary to transmit after compression), and complexity (equivalent to cost). In efforts to bring coding rate down to the required international standard of 8 kbit/s [Consultative Committee on International Telephony and Telegraphy (CCITT) standard], coding algorithms become more complex and hence take more time. Consequently a fourth criterion, communications delay, has become increasingly important for speech encoding. In a complex network, the delays of many encoders add together, transforming the delay into a significant impairment even after echo cancellation has been performed. The international CCITT standard specifies an algorithmic delay lower than 16 ms (with an objective of 5 ms) and a total coder-decoder delay of 32 ms (with an objective of 10 ms). The CCITT 16-kbit/s standard specifies a total delay lower than 2 ms. In mobile telephony, there are related objectives to get a frequency use efficiency in the range of 2-3 bps/Hz.

I found three other papers particularly interesting.

"Realization of Array Architectures for Hierarchical Block Matching Algorithms"

Yeu-Shen Jehng, Liang-Gee Chen,

Tzi-Dar Chiuch, Thou-Ho Chen Room 416

Department of Electrical

Engineering

National Taiwan University Taipei, Taiwan 10764, ROC

The basic problem being looked at in this paper (Jehng's thesis) is how to extract information from a twodimensional sequence of images in order to predict movement. For digital transmission of image data, it is much more efficient to transmit "motion vectors" rather than the primitive images, and

there are many algorithms that attempt to do this. Jehng has studied one particular method, the three-step hierarchical search algorithm (3HSA), which is very efficient in terms of operation count but is difficult to implement in hardware. In his paper he considers a technique due to H.T. Kung for a systolic array implementation of the algorithm. It is a nice piece of work but needs hardware implementation and testing to determine if it will be practical.

"Determination of IFS Codes Using
Scale-Space Correlation
Functions"
Masayuki Kawamata, Hiroaki
Kanbara, Tatsuo Higuchi
Department of Electronic
Engineering
Tohoku University

Aramaki, Aoba, Sendai 980, Japan E-mail: kambara@higuchi.ecei. tohoku.ac.jp

IFS (iterated function systems) have been very heavily studied in the context of image compression (M. Barnsley is one of its earliest and most active proponents, and of course work by B. Mandelbrot was seminal) for natural images. Kanbara's work involves the systemic analysis of fractal images and the development of an algorithm to determine the IFS codes using digital signal processing techniques. What makes this approach interesting is that while many clever people have been working on the topic of IFS, Kanbara's group is unique in their use of DSP thinking. In particular he proves an important theorem relating the maximum value (with respect to a parameter) of a one-parameter spatial correlation function to the IFS codes (when applied to binary images). Finally, his paper provides an algorithm implementing how the theorem can be applied.

"Application of High-Speed Analog
Neural Networks to Optical
Communication Systems"
Takao Matsumoto, Masafumi Koga,
Hiroshi Miyao, Yoshihito
Amemiya

NTT Transmission Systems
Laboratories
1-2356, Take

Yokosuka, Kanagawa 238-03, Japan
Tel: +81-468-59-3160
Fax: +81-462-40-2162

The main idea is to develop a neural net, optical WDM (wavelength demultiplexer). Typical optical WDM are difficult to fabricate and are not flexible. A single-mode transmission fiber allows multichannel signals to propagate through a multimode waveguide and couple to a detector array. When the optical signals are coherent the result is an inhomogeneous optical power distribution (speckle pattern) at the output caused by the interference among propagating modes. If this is input to a neural net (through a detector array) it might be possible to separate the signals as the output of the net. The advantages of this approach are that the optical components are easy to build and the demultiplexing characteristics can be changed by changing the neural net parameters, i.e., without changing the optical components. Matsumoto says it better, "In a fabrication sense, the burden which is imposed on the optics side in a conventional WDM demultiplexer is moved to the electronics side." His paper describes the experiments and an analog learning method [called multifrequency oscillation (MFO)]. The main problem with the approach is that more than 1K synapses/chip and a speed of over 1G input patterns per second are beyond the ability of current large scale integration (LSI) fabrication technology. Nevertheless, the technique is a very unusual one.

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