areas in this technology are depositing uniform semiconducting thin films over large areas, developing the necessary tools for deposition and further processing, improving the film electronic properties such as carrier mobility, keeping a high aperture ratio as pixel size is reduced, and reducing the overall process temperature so that lowcost substrates can be used. In a leadoff invited talk by H. Oshima and S. Morozumi of Seiko-Epson, the features of low-temperature (<600 °C) deposited poly-Si for high-resolution, high pixel density applications such as high definition TV (HDTV) valves (projection displays) were outlined. Their conclusion was that a-Si:H TFTs could be appropriate for large-area displays, but that poly-Si with its much higher mobilities and better device performance was essential for high-resolution liquid crystal display (LCD) applications. In follow-up poster papers, Seiko-Epson researchers also described poly-Si TFTs fabricated by using solid phase crystallization of very thin amorphous Si films and by XeCl pulsed excimer laser annealing of low-pressure chemical vapor deposited (LPCVD) poly-Si. The former technique is easily scaled up for production and yields films with carrier mobilities greater than 20 cm2/V-s without the need for hydrogenation and TFT on/off current ratios greater than 107. The laser anneal technique, while still experimental, yields electron mobilities of over 180 cm2/V-s and hole mobilities of over 60 cm2/V-s, thereby offering the possibility of selectively laser annealing sections of the film for the high-current driver TFTs and forming the matrix switching TFTs on the as-deposited sections with the corresponding low off current.

There were other papers demonstrating the efficacy of laser-annealed poly-Si TFTs. A group from NEC Corporation reported carrier mobilities similar to those of Seiko-Epson, and they had fabricated a 640-bit

complementary metal-oxide semiconductor (CMOS) shift register data driver operating at 1 MHz. Sony reported controlled grain growth by excimer laser anneal, leading to high carrier mobility as well as low leakage current (<0.02 pA/μm). They attributed their TFT performance enhancement to improved crystallinity in grains and reduced grain boundary trap density. Suggested applications include integrated stacked SRAMs and LCDs grated stacked SRAMS and LCDs built on low-melting-point glasses. M. Matsumara and coworkers from the Tokyo Institute of Technology presented work on a ramp-mode hydrogen radical beam annealing of lasercrystallized poly-Si and found electron mobility as high as 220 cm2/V-s. The importance of atomic hydrogen for grain boundary passivation in poly-Si has long been recognized by the TFT community and is believed a viable fabrication step in production. It is interesting to note that this contrasts with the general opprobrium extended to hydrogen in crystalline Si, despite a great deal of recent advances in the basic understanding of H in crystalline semiconductors. Of course, there is no room for controversy in the case of a-Si:H, since H is essential for its use as a dopable H is essential for its use as a dopable semiconductor. The Tokyo Institute of Technology group also demonstrated the efficacy of hydrogen radical annealing on hot-wall CVD-deposited amorphous Si TFTs. Another paper in the symposium dealing with H in poly-Si was that from Hiroshima University proposing a charge-pumping method for evaluation of the hydrogenation effect in poly-Si TFTs.

The Giant Microelectronics symposium also addressed alternatives to LCD materials used in the standard twisted nematic mode, where associated polarizers limit transmittance of the light valves and are heated by absorbed light. M. Yuki from Asahi Glass Company gave an invited talk on the use of an LC/polymer composite (LCPC)

material that operates in a scattering mode requiring no polarizers and at low driving voltages (6 V rms). Based on the LCPC they have fabricated a full-color projection TV with a utilization efficiency of incident light about four times that of conventional twisted nematic-based systems. Yet another use of polymers, this time as the active semiconductor TFT material, was reported in a presentation from Mitsubishi. While the best electron mobility (0.02 cm2/V-s) of this material is still an order of magnitude below that of even a-Si:H, the spin-coated polymeric semiconductor [poly(2,5thienylene) vinylene] offers potential for low cost and processing simplicity.

An alternative to the (threeterminal) TFT as the matrix switching element in LCD displays is a twoterminal nonlinear resistor. The latter does, of course, suffer from the inevitable absence of isolation between the drive and output signals but offers advantages such as no crossovers, no storage capacitor, fault tolerance, and fewer masking steps. K.E. Kuijk of Philips, Holland, presented an invited talk on the application of a-Si diodes for a full-color 6-inch TV display. He described a novel double diode plus reset circuit that has the same number of connections as a TFT active matrix LCD. Another two-terminal approach to the switching device was described by researchers from Toshiba who used metal-insulator-metal (MIM) structures based on anodic oxidation of a Ta thin film.

An innovative giant microelectronic technology using gravure printing techniques was presented by a group from Matsushita. Using glass intaglio and a silicon rubber roller, they were able to fabricate fine patterns on large areas (60 x 230 mm) with 10μm accuracy for use in a thermal printing head. Other papers presented in the symposium included a catalytic CVD process for poly-Si deposition at 410 °C [Tokyo

Institute of Technology], lowtemperature operation of poly-Si TFTs [Hiroshima University], and study of a noncrossing TFT matrix [Fujitsu]. A. Chiang et al. from Xerox, Palo Alto, reviewed in an invited talk the correlation between material preparation and processing parameters of poly-Si with the electronic properties of the active layer. She also addressed the role played by impurities in the crystallization process and the leakage mechanisms.

In summary, the symposium on Giant Microelectronics reflected the importance given to this area by the Japanese companies, spanning a wide spectrum beyond conventional micro- and optoelectronics. No major breakthroughs in terms of concepts or phenomena were reported, but the strong strides made in technology development were evident from the presentations.

SCIENCE AND TECHNOLOGY ON ULTRA-CLEAN WAFER PROCESSING

This symposium was intended to focus attention on the extreme necessity of contamination control as microelectronics "inches" towards nanoelectronics. The opening invited lecture was given by Prof. T. Ohmi of Tohoku University, who has been a pioneer in promoting and developing techniques for the preparation of ultra-clean surfaces characterized by the absence of particulates, organic and metallic contamination, native oxide, molecular adsorption, and surface microroughness. He stressed that such extremely stringent surface preparation steps are essential for establishing highperformance, low-temperature Si processing. In his presentation, he showed the influence of pH control of cleaning solutions on particle adhesion and surface microroughness. The role of particulate contamination on MOS interface properties is well known, but

surface microroughness was shown to be equally deleterious in terms of channel mobility reduction and MOS charge to failure. Ohmi also discussed the need to maintain the Si surface cleanliness and to activate a growing film on Si by using very low energy ion bombardment. Such an approach was reported to give nonalloyed Al/n*-Si ohmic contacts with lower contact resistance than the conventional airexposed process, Cu/Si Schottky diodes of near-ideal characteristics, and Cu interconnects with electromigration lifetime enhanced two to three orders of magnitude. In another invited paper given by Prof. C.R. Helms of Stanford University, it was pointed out that the chemistries for metal removal are strongly dependent on the Si surface chemistry (e.g., surface pretreatment step prior to metal incorporation) and step prior to metal incorporation) and the chemical environment of the metal impurities. The cleaning issue was further addressed by B.E. Deal et al. of ADVANTAGE Production Technology, Sunnyvale, CA, who described a single-wafer HF/H2O vapor cleaning system that yields better quality MOS interfaces compared to conventional aqueous cleans. Such "dry cleaning" aqueous cleans. Such "dry cleaning" systems are presently coming into vogue for environmental reasons (much less use of chemicals) as well as ready adaptability to cluster-type integrated processing.

An IBM effort in hydrogen fluoride (HF) and ultraviolet (UV) ozoneintegrated wafer cleaning was described in an invited talk by M. Liehr and S.R. Kasi. Their results show that foreign chemical species present at the surface in submonolayer levels can profoundly affect the quality of subsequently grown SiO, and hence the MOS parameters such as breakdown field, interface trap density, and radiation sensitivity. Their conclusion was that establishing correlations between detailed process chemistry and resulting device parameters is essential to understand, predict, and

control molecular contamination in future ultra large scale integration (ULSI). HF-treated Si surfaces were also discussed in other papers. An x-ray photoemission spectroscopy (XPS) study by Prof. M. Hirose's group in Hiroshima University extended previous work on H-terminated and F-terminated Si (111) surfaces and showed that suitable buffering of the HF solution was essential for obtaining a step-free, atomically flat surface that is chemically stable. A scanning transmission microscopy (STM) study of HF-treated Si (111) by researchers at the the Electrotechnical Laboratory revealed that a sample treated in 1% HF shows the SiH, phase, while a followup boil in hot water changes it to the SiH phase. This was verified independently by researchers from Fujitsu, who used infrared (IR) absorption spectroscopy.

The influence of contamination, passivating species as well as processinduced (plasma/ion bombardment) damage on that most precious of all interfaces, viz, Si/SiO,, and the p-n junction was addressed by a number of papers in this symposium. Y. Ono et al. from the NTT Atsugi Laboratories presented some very interesting new results on thermally diffused fluorine in SiO,. From Auger electron spectroscopy (AES) and secondary ion mass spectroscopy (SIMS) measurements, they found that the F-profile (obtained from an F-implanted layer) into SiO, sharply peaked at the Si/SiO, interface and abruptly dropped off inside Si. From electron spin resonance (ESR) measurements they also found the trivalent Si dangling bond density (Pb center) to fall with increasing F-dose, thus confirming fluorine passivation of the silicon/oxide interface traps. K. Machida et al., also from the NTT Atsugi Laboratories, presented an elegant technique for estimating charge buildup on gate oxide during plasma processing. Their method is based on the observation

that the oxidation of a metal film on

SiO2 is dependent on the electric field set up by the electrons diffusing from the SiO, surface to the metal. The latter, in turn, depends on the radio frequency (RF) bias, and they were able to correlate the gate oxide yield directly to the metal (Mo) oxide thickness measured by ellipsometry. Ohmi's group at Tohoku University also addressed the question of contamination in conventional ion implantation systems. They found that metal atoms in quantities on the order of 0.05% of the total dose are incorporated into ion-implanted wafers. With carefully installed sputtering protection boards, they were able to reduce the metallic contamination by a factor of 3. This directly translated into reduced p-n junction leakage under the desired low-temperature (<600 °C) post-implantation anneal. Using topographic, thermal wave, and atomic force imaging, researchers from Toshiba concluded that surface microroughness severely affected VLSI yield and reliability through oxide film degradation.

SURFACE ENGINEERING FOR SEMICONDUCTOR NANOSTRUCTURES

This symposium dealt with a number of topics concerning semiconductor surface passivation, heterointerface control, and atomic-scale characterization of interfaces. In a lead-off invited talk, F.J. Grunthaner of the Jet Propulsion Laboratory (JPL) reviewed atomicscale characterization and control and synthesis of semiconductor surfaces and interfaces. He described the features of strained layer epitaxial interfaces evaluated by a variety of techniques and emphasized the importance of interfacial roughness on superlattice systems. T. Saitoh et al. from Hokkaido University described a new technique to determine the surface state density of semiconductor surfaces by band-edge photoluminescence efficiency measurements. They showed examples of sulfur

passivation of GaAs surface and the use of a silicon interface control layer between SiO, and InGaAs. An alternative approach to surface state measurements was described by K. Hirose et al. from NEC Fundamental Research Laboratories. By using photoemission yield spectroscopy, where the resolution is limited only by the monochromator used (to 0.01 eV), they were able to demonstrate the changes in surface state density and distribution with surface preparation conditions.

In another invited talk on atomic imaging, atomic processing, and nanocharacterization, L.L. Kazmerski of the U.S. National Renewable Energy LaboU.S. National Renewable Energy Laboratory (NREL, formerly SERI) described the application of STM to generate patterns using lithography as well as to etch and to pattern surface structures. Nanoscale in-situ electrical characterization was also shown possicharacterization was also shown possible with the STM electron probe to map the minority-carrier current and conductivity variations. He showed conductivity variations. He showed "graphic" STM images of CuInSe, (a leading thin film solar cell material) before and after "nanoprocessing" with oxygen, followed by nanoscale electron beam induced current (NEBIC) response of CuInSe, grain boundaries with and without oxygen passivation. Carrying the work further, he showed the possibility of atomic-level engineering using a 3- to 5-mil-diameter catheter wire tip to introduce oxygen gas onto the surface. Using twin catheter onto the surface. Using twin catheter tips, one for imaging and the other for atomic processing, he presented excitatomic processing, he presented exciting results on the first atomic engineering on a semiconductor surface. The process makes possible (1) identification of specific atoms to be removed from the surface; (2) the removal of such atoms; (3) the placements of indisuch atoms; (3) the placements of individual, extrinsic atoms at those locations; and (4) comparison of the results on a bulk basis (using conventional EBIC) and on the nanoscale using NEBIC. Certainly, such atomic-scale processing plus characterization opens

up spectacular opportunities in a number of areas including semiconductor surface and grain boundary passivation, as well as atomic-scale defect engineering.

A different type of nanoscale processing technology using STM was described by researchers from Hiroshima University. By pulsing the negative bias on the STM tip in different ambient gases, they were able to form holes 25 Å in diameter and 7 Å deep and carbon dots 8 Å in diameter and 7 Å deep. Selective epitaxial growth of GaAs and AlGaAs to form quantum dots in a metal organic CVD (MOCVD) system was reported by a University of Tokyo group. Using in-plane atomic migration and changes in growth rates of the crystal planes, they were able to develop a novel technique for fabricating onedimensional weakly coupled quantum dots and GaAs dots surrounded in three dimensions by AlGaAs. A selective growth technique for GaAs molecular beam epitaxy (MBE) at growth temperatures as low as 550 °C was demonstrated by T. Sugaya et al. from the University of Tsukuba. By irradiating the growth surface with atomic hydrogen, they were able to enhance the Ga and As desorption rate from the SiO X or SiN masking surfaces, thus improving the growth selectivity.

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Selective-area epitaxy and pattern formation in III-V semiconductors through UHV processing for two- and three-dimensional nanostructures was also addressed in an invited paper by Y. Katayama et al. from the Tsukuba Optoelectronics Technology Research Laboratory. They described an ultrahigh vacuum (UHV) processing system with in situ electron beam (EB) lithography, EB-induced Cl2 etching of GaAs, and selective-area growth of GaAs using an SiO, mask. Lateral epitaxy [by metal organic MBE (MOMBE)] on maskless, patterned GaAs substrates was described in a paper from another group in the same laboratory. By suitable control of growth conditions, they were able to confine

the growth to the sidewall. This technique is clearly attractive for advanced device structures such as those based on quantum wires.

Chemical treatment of compound semiconductor surfaces has attracted a great deal of attention ever since the demonstration a few years ago that simple aqueous S and Se treatments of GaAs can be remarkably effective in passivating nonradiative defect centers at the surface. This, in turn, reduces the surface recombination velocity for excess carriers and improves the performance of minority-carrier devices in practical devices such as bipolar transistors and solar cells. These results also spawned interest in the study of such chemical passivation steps at metalsemiconductor (Schottky barrier) and semiconductor heterojunction interfaces, both from possible applications in interfacial electrical barrier control and understanding the nature of interface Fermi level pinning. A good part of this symposium was hence devoted to this topic of surface/interface passivation. In the lead invited talk on this topic, C.G. Sandroff of Bellcore provided a review of the S and Se passivation results on GaAs, followed by recent results on reliability enhancement of InGaAsP laser diodes (under electrostatic discharge) under such surface chemical passivation. By using in situ photoluminescence (PL) in an MBE chamber, he showed it is possible to gain new insights into the passivation mechanism, e.g., which type of surface reconstruction is best for reducing surface recombination. Sandroff further pointed out that the in situ PL probe (through the dependence of PL peak on temperature) offers the bonus feature of measuring the substrate temperature. Precise measurement of wafer temperature during processing has always been a tricky problem, and this PL-based technique is currently being developed for incorporation in plasma processing and other equip

ment.

There were a number of papers dealing with surface/interface passivation of III-V semiconductors. O.S. Nakagawa et al. from the Pennsylvania State University reported on the results of an Au/GaAs Schottky interface modified by a self-assembled interface modified by a self-assembled monolayer of conformationally ordered monolayer of conformationally ordered octadecyl thiol. They reported enhanced barrier height on n-GaAs with no changes in diode ideality factor, implying the barrier modification is essentially due to modification of interface states and not due to any residual oxide layer. Incidentally, this apparently is the first report of a self-assembled monolayer film formed on any semiconductor. C.G. Choi et al. from Hyundai R&D Center described a forward-bias capacitance spectroscopy technique for Schottky diodes that could be used to evaluate the effectiveness of interface passivation schemes by measuring the interfacial trap distribution. By incorporating a monolayer sulfur passivating film (followed by epi AlGaAs blocking and capping layers) in a surfaceemitting, buried heterostructure laser diode, Tamanuki et al. from the Tokyo Institute of Technology were able to demonstrate an order of magnitude reduction in the surface recombination velocity on the sidewall of the active layer.

The application of sulfur passivation to the heterointerface between ZnSe-based II-VI semiconductors [of intense current interest for blue lightemitting diodes (LEDs)] and GaAs was discussed in a paper by T. Ohnakado et al. from Kyoto University. In an interesting new application of the S treatment, they report that the sulfur treatment of GaAs prior to the II-VI growth could improve the optical properties of the II-VI epi material. They also found nearly ideal capacitancevoltage (C-V) characteristics for Au/ZnSe/p-GaAs metal-insulatorsemiconductor (MIS) structures, perhaps offering yet another chance for

obtaining the ever-elusive GaAs MIS field effect transistor (MISFET).

A novel heterostructure based on amorphous Se on GaAs was investigated by S. Takatani et al. from the Hitachi Central Research Laboratories. The impetus for studying this unusual system stems from the Se passivation of the GaAs interface, coupled with the interesting semiconducting properties of a-Se. They found a staggered band alignment with a small barrier for holes, suggesting potential development of an efficient avalanche photodiode structure (with tunable bandgap if the GaAs substrate is replaced by Al Ga, As).

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R.H. Williams of Cardiff presented an invited paper that dealt with both heterointerface modification and atomic-scale characterization. He reported on 8-doped InAs/GaAs and Al/n-GaAs interfaces, evaluated by both electrical measurements and by the recently developed ballistic electron emission microscopy (BEEM) technique. He showed that a Be d-doped layer could increase the interfacial barrier height substantially, just as a Si d-doped layer could decrease the barrier height.

ADVANCED MATERIALS FOR GIGA-SCALE ENGINEERING

This symposium essentially addressed new nonsemiconductor materials needed to enhance the performance of Si microelectronics as the frontiers are being pushed into the giga-scale integration levels. The materials proposed include those for interconnects, diffusion barriers, high dielectric constant insulators, and contacts.

The first invited paper in this symposium was on plasma-enhanced CVD (PECVD) TiN, given by A. Sherman of Varian Research Center. Sputterdeposited TiN has been found to be highly adherent to Si, while offering