Software and Compilers for Embedded Systems: 7th International Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003, ProceedingsAndreas Krall Springer, 2003. gada 24. okt. - 406 lappuses This volume contains the proceedings of the 7th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2003, held in Vienna, Austria, September 2426, 2003. Initially, the workshop was referred to as the International Workshop on Code Generation for Embedded Systems. The ?rst workshop took place in 1994 in Schloss Dagstuhl, Germany. From its beg- nings, the intention of the organizers was to create an atmosphere in which the researcherscould participateactively in dynamic discussionsand pro?t from the assembly of international experts in the ?eld. It was at the fourth workshop, in St. Goar, Germany, in 1999, that the spectrum of topics of interest for the workshop was extended, and not only code generation, but also software and compilers for embedded systems, were considered. The change in ?elds of interest led to a change of name, and this is when the present name was used for the ?rst time. Since then, SCOPES has been held again in St. Goar, Germany, in 2001; Berlin, Germany, in 2002; and this year, 2003, in Vienna, Austria. In response to the call for papers, 43 very strong papers from all over the world were submitted. The program committee selected 26 papers for pres- tation at SCOPES 2003. All submitted papers were reviewed by at least three experts in order to ensure the quality of the work presented at the workshop. |
No grāmatas satura
1.5. rezultāts no 39.
x. lappuse
... Partitioning for DSP Software Synthesis ........................ 344 Ming-Yung Ko and Shuvra S. Bhattacharyya Efficient Variable Allocation for Dual Memory Banks of DSPs .......... 359 Viera Sipkova Cache Behavior Modeling of Codes with ...
... Partitioning for DSP Software Synthesis ........................ 344 Ming-Yung Ko and Shuvra S. Bhattacharyya Efficient Variable Allocation for Dual Memory Banks of DSPs .......... 359 Viera Sipkova Cache Behavior Modeling of Codes with ...
4. lappuse
... partitioning the data path into clusters with local registers [3] [6], little work has been done on using global registers for the communication among clusters. MAJC, a scalable microprocessor from SUN [8], is one of them. In MAJC, each ...
... partitioning the data path into clusters with local registers [3] [6], little work has been done on using global registers for the communication among clusters. MAJC, a scalable microprocessor from SUN [8], is one of them. In MAJC, each ...
5. lappuse
... partitioning, has been performed. Later in Section 6, this assumption is released. In many clustered architectures, there is only one functional unit per type in a cluster. Therefore assigning operations to functional units [2] is ...
... partitioning, has been performed. Later in Section 6, this assumption is released. In many clustered architectures, there is only one functional unit per type in a cluster. Therefore assigning operations to functional units [2] is ...
6. lappuse
... partitioning. Otherwise, operation assignment still has to be performed within one range or cluster. Range S1 and range S2 share registers r1 and r2. Values produced by FU1 or FU2 and consumed by FU3 or FU4 are stored in r1 or r2, and ...
... partitioning. Otherwise, operation assignment still has to be performed within one range or cluster. Range S1 and range S2 share registers r1 and r2. Values produced by FU1 or FU2 and consumed by FU3 or FU4 are stored in r1 or r2, and ...
14. lappuse
... partitioning each range into smaller overlapping ranges. Table 2 shows the results for a four-range LAR architecture. In this table, columns 2 to 4 report the code size for the central register file architecture and the LAR architecture ...
... partitioning each range into smaller overlapping ranges. Table 2 shows the results for a four-range LAR architecture. In this table, columns 2 to 4 report the code size for the central register file architecture and the LAR architecture ...
Saturs
1 | |
17 | |
33 | |
Sheayun Lee Jaejin Lee Sang Lyul Min Jason Hiser | 47 |
Erik Eckstein Oliver König and Bernhard Scholz | 66 |
Reconstructing Control Flow from Predicated Assembly Code | 81 |
Loop Optimizations | 101 |
Stefaan Himpe Francky Catthor and Geert Deconinck | 117 |
Code Generation for Packet Header Intrusion Analysis on the IXP1200 | 226 |
Register Allocation | 240 |
FineGrain Register Allocation Based on a Global Spill Costs Analysis | 255 |
Offset Assignment | 270 |
Improving Offset Assignment through Simultaneous Variable Coalescing | 285 |
Desiree Ottoni Guilherme Ottoni Guido Araujo and Rainer Leupers | 298 |
Performance Analysis for Identification of SubTaskLevel Parallelism | 313 |
Towards Superinstructions for Java Interpreters | 329 |
Litong Song Krishna Kavi and Ron Cytron | 133 |
Automatic Retargeting | 151 |
Extraction of Efficient Instruction Schedulers from CycleTrue | 167 |
System Design | 182 |
Arshad Jhumka Neeraj Suri and Martin Hiller | 198 |
Composable Code Generation for ModelBased Development | 211 |
Kevin Casey David Gregg M Anton Ertl and Andrew Nisbet | 344 |
Efficient Variable Allocation for Dual Memory Banks of DSPs | 359 |
Cache Behavior Modeling of Codes with DataDependent Conditionals | 373 |
A Fast Instruction Cache Optimizer | 388 |
Author Index | 403 |
Citi izdevumi - Skatīt visu
Software and Compilers for Embedded Systems: 7th International Workshop ... Andreas Krall Ierobežota priekšskatīšana - 2003 |
Software and Compilers for Embedded Systems: 7th International Workshop ... Andreas Krall Priekšskatījums nav pieejams - 2003 |
Bieži izmantoti vārdi un frāzes
abstract access graph access sequence algorithm analysis applications approach architecture basic block benchmarks bytecode cache call graph coloring compiler complex component Computer conflict graph constraints control flow control flow graph cost cycle defined denote digital signal processors Earl Gray edges embedded processors embedded systems evaluation example execution flow facts flow graph framework function Galois connection heuristic implemented input instruction selection instruction set interference graph interpreter iteration Java Java Virtual Machine Leupers loop memory banks meta-information method node nop IF r1 offset assignment operand operations optimization parallel partitioning path PBQP performance predicated problem profiling proposed r1 nop reconstruction recursive reduced instruction reference register allocation register file represents requires retargetable safety specification scheduler Section semantics SIMD SIMD instructions spill SSA-graph structure superinstructions target techniques thread tion tool transformation tree uEngine update vector VLIW WCET ZOLB