Low-Energy FPGAs — Architecture and DesignSpringer Science & Business Media, 2012. gada 6. dec. - 182 lappuses Low-Energy FPGAs: Architecture and Design is a primary resource for both researchers and practicing engineers in the field of digital circuit design. The book addresses the energy consumption of Field-Programmable Gate Arrays (FPGAs). FPGAs are becoming popular as embedded components in computing platforms. The programmability of the FPGA can be used to customize implementations of functions on an application basis. This leads to performance gains, and enables reuse of expensive silicon. Chapter 1 provides an overview of digital circuit design and FPGAs. Chapter 2 looks at the implication of deep-submicron technology onFPGA power dissipation. Chapter 3 describes the exploration environment to guide and evaluate design decisions. Chapter 4 discusses the architectural optimization process to evaluate the trade-offs between the flexibility of the architecture, and the effect on the performance metrics. Chapter 5 reviews different circuit techniques to reduce the performance overhead of some of the dominant components. Chapter 6 shows methods to configure FPGAs to minimize the programming overhead. Chapter 7 addresses the physical realization of some of the critical components and the final implementation of a specific low-energy FPGA. Chapter 8 compares the prototype array to an equivalent commercial architecture. |
Saturs
| 2 | |
COMPUTATION MODEL | 17 |
IMPACT OF POWER DISSIPATION | 32 |
EXPLORATION ENVIRONMENT | 43 |
EXTRACTION | 66 |
GOAL OF INTERCONNECT OPTIMIZATION | 81 |
CIRCUIT TECHNIQUES | 95 |
CLOCK DISTRIBUTION | 105 |
CONFIGURATION ENERGY COMPONENTS | 118 |
TILE LAYOUT | 137 |
RESULTS | 151 |
CONCLUSION | 161 |
INDEX | 179 |
Citi izdevumi - Skatīt visu
Low-Energy FPGAs — Architecture and Design Varghese George,Jan M. Rabaey Ierobežota priekšskatīšana - 2001 |
Low-Energy FPGAs — Architecture and Design Varghese George,Jan M. Rabaey Priekšskatījums nav pieejams - 2012 |
Low-Energy FPGAs - Architecture and Design Varghese George,Jan M Rabaey Priekšskatījums nav pieejams - 2001 |
Bieži izmantoti vārdi un frāzes
3-input LUTs 5-input algorithm antifuse application ASIC Chapter chip circuit clock distribution network clock energy components computing configuration bits configuration energy configuration storage connection box cost datapath decoder diffusion capacitance dominant double-edge-triggered energy consumption energy dissipated energy efficiency Energy-Delay Product evaluate Field-Programmable Gate Arrays Figure flexibility flip-flops FPGA environment frequency general-purpose processor GSMT heuristic IKMB implementation improve increase input pin interconnect architecture Level-0 logic block logic capacity LOGIC LOGIC LOGIC lookup table low-energy FPGA LP_PGAII Manhattan distance memory cells Mesh structure method netlist nets nodes optimization output pins path length performance accelerator placement and routing power dissipation programming the FPGA prototype realize reconfigurable reconfigurable computing reduce the number routing channel routing resources routing segments routing switches satellite shift register shown in Fig simulated annealing speed performance SRAM STMicroelectronics switch box Symmetric Mesh architecture target architecture tile total energy tracks transistors tree weighted graph Xilinx