LCPC'97, 9. sējumsDavid Sehr Springer Science & Business Media, 1997. gada 11. jūn. - 612 lappuses This book presents the thoroughly refereed post-workshop proceedings of the 9th International Workshop on Languages and Compilers for Parallel Computing, LCPC'96, held in San Jose, California, in August 1996. The book contains 35 carefully revised full papers together with nine poster presentations. The papers are organized in topical sections on automatic data distribution and locality enhancement, program analysis, compiler algorithms for fine-grain parallelism, instruction scheduling and register allocation, parallelizing compilers, communication optimization, compiling HPF, and run-time control of parallelism. |
Saturs
CrossLoop Reuse Analysis and Its Application to Cache Optimizations | 1 |
Locality Analysis for Distributed SharedMemory Multiprocessors | 20 |
Data Distribution and Loop Parallelization for SharedMemory Multiprocessors | 41 |
Data Localization Using Loop Aligned Decomposition for MacroDataflow Processing | 56 |
Exploiting Monotone Convergence Functions in Parallel Programs | 75 |
Exact versus Approximate Array Region Analyses | 86 |
ContextSensitive Interprocedural Analysis in the Presence of Dynamic Aliasing | 101 |
Initial Results for Glacial Variable Analysis | 120 |
StatementLevel CommunicationFree Partitioning Techniques for Parallelizing Compilers | 389 |
Generalized Overlap Regions for Communication Optimization in DataParallel Programs | 404 |
Optimizing the Representation of Local Iteration Sets and Access Sequences for BlockCyclic Distributions | 420 |
Interprocedural Array Redistribution DataFlow Analysi | 435 |
Early Experience | 450 |
Simple Qualitative Experiments with a Spars Compiler | 466 |
A Unique Approach to Compiling Array Languages for Parallel Machines | 481 |
Compilation of Constraint Systems to Procedural Parallel Programs | 501 |
Predicated Code Optimizations | 135 |
Determining Asynchronous Pipeline Execution Times | 154 |
Compiler Techniques for Concurrent Multithreading with Hardware Speculation Support | 175 |
ResourceDirected Loop Pipelining | 192 |
Integrating Program Optimizations and Transformations with the Scheduling of Instruction Level Parallelism | 207 |
A New Global Code Scheduling Approach | 222 |
Parametric Computation of Margins and of Minimum Cumulative Register Lifetime Dates | 231 |
Global Register Allocation Based on Graph Fusion | 246 |
Automatic Parallelization for Noncache Coherent Multiprocessors | 266 |
Eliminating Lock Overhead in Automatically Parallelized ObjectBased Programs | 285 |
Are Parallel Workstations the Right Target for Parallelizing Compilers? | 300 |
Optimal Reordering and Mapping of a Class of Nested Loops for Parallel Execution | 315 |
CommunicationMinimal Tiling of Uniform Dependence Loops | 330 |
CacheCoherent DistributedMemory Multiprocessors | 350 |
ResourceBased Communication Placement Analysis | 369 |
A Multithreaded Substrate and Compilation Model for the Implicitly Parallel Language pH | 519 |
Threads for Interoperable Parallel Programming | 534 |
A Programming Environment for Dynamic Resource Allocation and Data Distribution | 553 |
Dependence Driven Execution for Data Parallelism | 570 |
oSSA and Its Construction Through Symbolic Interpretation | 585 |
Extended Abstract | 588 |
3D Visualization of Program Structure and Data Dependence for Parallelizing Compilers and Parallel Programming | 591 |
Side Effect Analysis on UserDefined Reduction Functions with Dynamic PointerLinked Data Structures | 594 |
Estimating Minimum Execution Time of Perfect Loop Nests with LoopCarried Dependences | 597 |
Automatic Data and Computation Partitioning on Scalable Shared Memory Multiprocessors | 600 |
The Loop Parallelizer LooPoAnnouncement | 603 |
A Generalized forall Concept for Parallel Languages | 605 |
Memory Optimizations In The Intel Reference Compiler | 608 |
Author Index | 611 |
Citi izdevumi - Skatīt visu
Languages and Compilers for Parallel Computing David Sehr,Utpal Banerjee,David Gelernter Priekšskatījums nav pieejams - 2014 |
Bieži izmantoti vārdi un frāzes
algorithm aliasing analysis application architecture array reference assignment basic block buffer cache misses communication communication-free constraint control flow cost Cray T3D cycle data dependence data partitions data structures data-flow data-flow analysis dependence graph Doall dynamic edges efficient elements ENDDO example execution Figure Fortran framework function global High Performance Fortran hyperplane implementation integer interference graph interprocedural iteration space live range lock coarsening loop body loop fusion loop nest machine macrotasks mapping matrix message passing method multiple multiprocessors node non-local number of processors operations optimal tilings overhead Parallel Computing parallel loops parallel programs performance phase pipeline placement Polaris predicate prefetch problem proc procedure Programming Languages RDLP redistribution reduce region register allocation resource reuse run-time sequential shared memory solution sparse matrix speedup spill statement-iteration static subroutine superblock superthreaded synchronization task techniques thread tion transformations values variables vector VLIW
Populāri fragmenti
583. lappuse - Schauser, Thorsten von Eicken and John Wawrzynek. Fine-grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine. In Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 1991.