Functional Verification of Programmable Embedded Architectures: A Top-Down Approach

Pirmais vāks
Springer Science & Business Media, 2005 - 180 lappuses
It is widely acknowledged that the cost of validation and testing comprises a s- nificant percentage of the overall development costs for electronic systems today, and is expected to escalate sharply in the future. Many studies have shown that up to 70% of the design development time and resources are spent on functional verification. Functional errors manifest themselves very early in the design flow, and unless they are detected up front, they can result in severe consequence- both financially and from a safety viewpoint. Indeed, several recent instances of high-profile functional errors (e. g. , the Pentium FDIV bug) have resulted in - creased attention paid to verifying the functional correctness of designs. Recent efforts have proposed augmenting the traditional RTL simulation-based validation methodology with formal techniques in an attempt to uncover hard-to-find c- ner cases, with the goal of trying to reach RTL functional verification closure. However, what is often not highlighted is the fact that in spite of the tremendous time and effort put into such efforts at the RTL and lower levels of abstraction, the complexity of contemporary embedded systems makes it difficult to guarantee functional correctness at the system level under all possible operational scenarios. The problem is exacerbated in current System-on-Chip (SOC) design meth- ologies that employ Intellectual Property (IP) blocks composed of processor cores, coprocessors, and memory subsystems. Functional verification becomes one of the major bottlenecks in the design of such systems.

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Saturs

Introduction
3
112 Functional Verification A Challenge
4
12 Traditional Validation Flow
8
13 TopDown Validation Methodology
10
14 Book Organization
12
Architecture Specification
13
ARCHITECTURE SPECIFICATION
15
21 Architecture Description Languages
16
44 Related Work
80
45 Chapter Summary
81
Design Validation
83
51 Property Checking using Symbolic Simulation
85
52 Equivalence Checking
87
53 Experiments
88
532 Equivalence Checking of the DLX Architecture
91
54 Related Work
92

211 Behavioral ADLs
18
212 Structural ADLs
19
214 Partial ADLs
20
23 Specification using EXPRESSION ADL
21
231 Processor Specification
24
232 Coprocessor Specification
25
233 Memory Subsystem Specification
27
24 Chapter Summary
28
Validation of Specification
29
31 Validation of Static Behavior
30
311 Graphbased Modeling of Pipelines
31
312 Validation of Pipeline Specifications
34
313 Experiments
45
32 Validation of Dynamic Behavior
48
322 Validation of Dynamic Properties
54
323 A Case Study
59
33 Related Work
61
34 Chapter Summary
62
TopDown Validation
63
Executable Model Generation
65
41 Survey of Contemporary Architectures
66
412 Similarities and Differences
68
42 Functional Abstraction
69
422 Behavior of a Generic Processor
73
423 Structure of a Generic Memory Subsystem
74
425 Interrupts and Exceptions
75
43 Reference Model Generation
77
55 Chapter Summary
93
Function Test Generation
95
611 Test Generation Methodology
96
612 A Case Study
99
62 Functional Coverage driven Test Generation
103
622 Functional Coverage Estimation
105
623 Test Generation Techniques
106
624 A Case Study
112
63 Related Work
116
64 Chapter Summary
117
Future Directions
119
Conclusion
121
72 Future Directions
122
Appendices
125
Survey of Comtemporary ADLs
127
A2 Behavioral ADLs
130
A3 Mixed ADLs
134
A4 Partial ADLs
139
Specification of DLX Processor
141
Interrupts Exceptions in ADL
147
Validation of DLX Specifications
151
Design Space Exploration
155
EI Simulator Generation and Exploration
156
E2 Hardware Generation and Exploration
162
References
167
Index
179
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