The Student's Guide to VHDL
Elsevier Science, 1998. gada 15. janv. - 336 lappuses
VHDL is a language for describing digital electronic systems. A vital, efficient step in the system design process, VHDL allows for the design and simulation of a hardware system prior to it actually being manufactured.
Offering the same clear, accessible style as The Designer's Guide to VHDL, The Student's Guide is designed as a main text for introductory VHDL courses, and as a supplementary text for courses that require VHDL-based project work, such as computer architecture, digital design, and digital logic courses. This new condensed text also serves as a quick, self-teaching guide for practicing engineers who need to learn only the basics of VHDL.
1.3. rezultāts no 55.
Some entities may be designed to allow inputs to be left open by specifying a
default value for a port . When the entity is instantiated , we can specify that a port
is to be left open by using the keyword open in the port association list , as shown
Summary of Procedure Parameters Let us now summarize all that we have seen
in specifying and using parameters for procedures . The syntax rule on page 166
shows that we can specify five aspects of each formal parameter . First , we may ...
... to specify the propagation delay from clock rising edge to output , Tsu _ d _ clk
to specify the setup time of data before a clock edge and Th _ d _ clk to specify
the hold time of data after a clock edge . The values of these generic constants
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