The Student's Guide to VHDL
Elsevier Science, 1998. gada 1. janv. - 336 lappuses
VHDL is a language for describing digital electronic systems. A vital, efficient step in the system design process, VHDL allows for the design and simulation of a hardware system prior to it actually being manufactured.
Offering the same clear, accessible style as The Designer's Guide to VHDL, The Student's Guide is designed as a main text for introductory VHDL courses, and as a supplementary text for courses that require VHDL-based project work, such as computer architecture, digital design, and digital logic courses. This new condensed text also serves as a quick, self-teaching guide for practicing engineers who need to learn only the basics of VHDL.
1.3. rezultāts no 26.
Selected Signal Assignment Statements The selected signal assignment statement is similar in many ways to the conditional signal assignment statement . It , too , is a shorthand for a number of ordinary signal assignments embedded in a ...
Apart from the difference in the equivalent process , the selected signal assignment is similar to the conditional assignment . Thus the special waveform unaffected can be used to specify that no assignment take place for some values of ...
Note that we have to use selected names to refer to the subtype address , the type status_value , the enumeration literals of status_value and the implicitly declared " = " operator , defined in the package cpu_types .
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Scalar Data Types and Operations
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