The Student's Guide to VHDL
Elsevier Science, 1998. gada 15. janv. - 336 lappuses
VHDL is a language for describing digital electronic systems. A vital, efficient step in the system design process, VHDL allows for the design and simulation of a hardware system prior to it actually being manufactured.
Offering the same clear, accessible style as The Designer's Guide to VHDL, The Student's Guide is designed as a main text for introductory VHDL courses, and as a supplementary text for courses that require VHDL-based project work, such as computer architecture, digital design, and digital logic courses. This new condensed text also serves as a quick, self-teaching guide for practicing engineers who need to learn only the basics of VHDL.
1.3. rezultāts no 27.
Selected Signal Assignment Statements The selected signal assignment
statement is similar in many ways to the conditional signal assignment statement
. It , too , is a shorthand for a number of ordinary signal assignments embedded in
Note that we have to use selected names to refer to the subtype address , the
type status _ value , the enumeration literals of status _ value and the implicitly
declared = operator , defined in the package cpu _ types . This is because they
3 Use Clauses We have seen how we can refer to an item provided by a package
by writing its selected name , for example , work . cpu _ types . status _ value .
This name refers to the item status _ value in the package cpu _ types stored in ...
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