The Student's Guide to VHDL
Elsevier Science, 1998. gada 1. janv. - 336 lappuses
VHDL is a language for describing digital electronic systems. A vital, efficient step in the system design process, VHDL allows for the design and simulation of a hardware system prior to it actually being manufactured.
Offering the same clear, accessible style as The Designer's Guide to VHDL, The Student's Guide is designed as a main text for introductory VHDL courses, and as a supplementary text for courses that require VHDL-based project work, such as computer architecture, digital design, and digital logic courses. This new condensed text also serves as a quick, self-teaching guide for practicing engineers who need to learn only the basics of VHDL.
1.3. rezultāts no 57.
DRAM_controller ( fpld ) port map ( cpu_rd , cpu_wr , cpu_mem , mem_ras , mem_cas , mem_we , cpu_rdy ) ; In this example , the name work refers to the current working library in which entities and architecture bodies are stored .
A component instantiation using this entity might appear as follows : signal in_data , out_data : bit_vector ( 0 to bus_size - 1 ) ; - ok_reg : entity work.reg generic map ( width = > bus_size ) port map ( d = > in_data , q = > out_data ...
... Tsetup , Thold : delay_length ) ; port ( clk : in bit ; clr : in bit ; d : in bit ; q : out bit ) ; end component flipflop ; begin bito : component flipflop generic map ( Tprop = > 2 ns , Tsetup = > 2 ns , Thold = > 1 ns ) port map ...
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