The Student's Guide to VHDLElsevier Science, 1998. gada 15. janv. - 312 lappuses VHDL is a language for describing digital electronic systems. A vital, efficient step in the system design process, VHDL allows for the design and simulation of a hardware system prior to it actually being manufactured. Offering the same clear, accessible style as The Designer's Guide to VHDL, The Student's Guide is designed as a main text for introductory VHDL courses, and as a supplementary text for courses that require VHDL-based project work, such as computer architecture, digital design, and digital logic courses. This new condensed text also serves as a quick, self-teaching guide for practicing engineers who need to learn only the basics of VHDL.
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1.–3. rezultāts no 57.
... port of the entity either with one signal of the enclosing architecture body ... map ( cpu_rd , cpu_wr , cpu_mem , mem_ras , mem_cas , mem_we , cpu_rdy ) ... port map of this example lists the signals in the enclosing architecture body to ...
... ports . A component instantiation using this entity might ap- pear as follows : signal in_data , out_data : bit_vector ( 0 to bus_size - 1 ) ; ok_reg entity work.reg generic map ( width = > bus_size ) port map ( d = > in_data , q ...
... map ( Tprop = > 2 ns , Tsetup = > 2 ns , Thold = > 1 ns ) port map ( clk = > clk , clr = > clr , d = > d ( 0 ) , q = > q ( 0 ) ) ; bit1 component flipflop generic map ( Tprop = > 2 ns , Tsetup = > 2 ns , Thold = > 1 ns ) port map ( clk ...
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Fundamental Concepts | 1 |
X | 22 |
A Scalar Data Types and Operations | 27 |
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Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication Hubert Kaeslin Ierobežota priekšskatīšana - 2008 |