The Student's Guide to VHDL
Elsevier Science, 1998. gada 15. janv. - 336 lappuses
VHDL is a language for describing digital electronic systems. A vital, efficient step in the system design process, VHDL allows for the design and simulation of a hardware system prior to it actually being manufactured.
Offering the same clear, accessible style as The Designer's Guide to VHDL, The Student's Guide is designed as a main text for introductory VHDL courses, and as a supplementary text for courses that require VHDL-based project work, such as computer architecture, digital design, and digital logic courses. This new condensed text also serves as a quick, self-teaching guide for practicing engineers who need to learn only the basics of VHDL.
1.3. rezultāts no 51.
In the parameter interface list we have identified one formal parameter named op
. This name is used in the statements in the procedure to refer to the value that
will be passed as an actual parameter when the procedure is called . The mode
When the procedure returns , the values assigned by the procedure to the formal
parameters result and overflow are used to update the ... For an out mode ,
variable - class parameter , the caller must supply a variable as an actual
During execution of the model , the process packet _ assembler calls the
procedure receive _ packet , passing the signals recovered _ data and recovered
_ clock as actual parameters . We can think of the procedure as executing " on
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