The Student's Guide to VHDL
Elsevier Science, 1998. gada 15. janv. - 336 lappuses
VHDL is a language for describing digital electronic systems. A vital, efficient step in the system design process, VHDL allows for the design and simulation of a hardware system prior to it actually being manufactured.
Offering the same clear, accessible style as The Designer's Guide to VHDL, The Student's Guide is designed as a main text for introductory VHDL courses, and as a supplementary text for courses that require VHDL-based project work, such as computer architecture, digital design, and digital logic courses. This new condensed text also serves as a quick, self-teaching guide for practicing engineers who need to learn only the basics of VHDL.
1.3. rezultāts no 35.
FIGURE 8 - 9 library ieee ; use ieee . std _ logic _ 1164 . all ; entity bus _ module
is port ( synch : inout std _ ulogic ; . . . ) ; end entity bus _ module ; architecture top
_ level of bus _ based _ system is signal synch _ control : std _ logic ; . . . begin ...
3 ] Below is a timing diagram for the system with two bus modules using the wired
- and synchronization signal described in ... Indicate the times at which each bus
module proceeds with its internal operation , as described in Figure 8 - 10 .
A component declaration , on the other hand , defines a virtual , or idealized ,
module that is included within an architecture body . It is as though we are
saying , For this architecture body , we assume there is a module as defined by
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