The Student's Guide to VHDL

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Elsevier Science, 1998. gada 15. janv. - 336 lappuses
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VHDL is a language for describing digital electronic systems. A vital, efficient step in the system design process, VHDL allows for the design and simulation of a hardware system prior to it actually being manufactured.
This new book provides a tutorial
introduction to the fundamental modeling features of VHDL and shows how the features are used for the design of digital systems.

Offering the same clear, accessible style as The Designer's Guide to VHDL, The Student's Guide is designed as a main text for introductory VHDL courses, and as a supplementary text for courses that require VHDL-based project work, such as computer architecture, digital design, and digital logic courses. This new condensed text also serves as a quick, self-teaching guide for practicing engineers who need to learn only the basics of VHDL.

* On-line resources include code for case studies.
* Numerous exercises that are coded for difficulty and expected solution time. * Solutions to the level one exercises are included in the book for self-testing.
* An appendix citing the differences between the 1987 standard and the 1993 standard which is described in the book.

No grāmatas satura

 

1.–3. rezultāts no 87.

104. lappuse
The syntax rules for this simplified form of entity declaration are entity _
declaration = entity identifier is [ port ( port _ interface _ list ) ; ] { entity _
declarative _ item } end [ entity ] [ identifier ) ; interface _ list = ( identifier { , . . . } : [
mode ) subtype _ ...
234. lappuse
... procedure _ call _ statement \ passive _ process _ statement } ] end [ entity ] [
identifier ) ; The difference between this and the simpler rule we have seen
before is the inclusion of the optional generic interface list before the port
interface list .
239. lappuse
FIGURE 9 - 3 entity reg is generic ( width : positive ) ; port ( d : in bit _ vector ( O to
width - 1 ) ; q : out bit _ vector ( 0 to width - 1 ) ; clk , reset : in bit ) ; end entity reg ;
architecture behavioral of reg is begin behavior : process ( clk , reset ) is ...

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Saturs

Fundamental Concepts
1
Exercises
25
Exercises
51
Autortiesības

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The Student's Guide to VHDL
Peter J. Ashenden
Ierobežota priekšskatīšana - 1998

Bieži izmantoti vārdi un frāzes

actual allows alternative applied architecture body array array type assertion association attribute begin behavioral binding bit_vector boolean called changes Chapter character clause clock component instance concurrent condition configuration connected constant contains corresponding counter defined delay described determine digit downto driver elements end architecture end entity end loop end process entity declaration example executed expression false Figure formal function identifier implementation indicates initial input instantiation integer interface keyword label language literal logic look loop memory mode module Note operand operators outline output package parameter passed port map position procedure range record refer represent resolved result scheduled selected shown in Figure shows signal assignment statement simple simulation specify std_ulogic string structural subtype syntax rule term tion transaction true unit variable vector VHDL write

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Par autoru (1998)

Peter J. Ashenden received his B.Sc.(Hons) and Ph.D. from the University of Adelaide, Australia. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. His research interests are computer organization and electronic design automation. Dr. Ashenden is also an independent consultant specializing in electronic design automation (EDA). He is actively involved in IEEE working groups developing VHDL standards, is the author of The Designer's Guide to VHDL and The Student's Guide to VHDL and co-editor of the Morgan Kaufmann series, Systems on Silicon. He is a senior member of the IEEE and a member of the ACM.

Bibliogrāfiskā informācija

QR code for The Student's Guide to VHDL
NosaukumsThe Student's Guide to VHDL
Systems on Silicon
AutorsPeter J. Ashenden
IzdevējsElsevier Science, 1998
Oriģināls noMičiganas universitāte
Digitalizēta13.12.2007
ISBN1558605207, 9781558605206
Apjoms336 lappuses
  
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