The Student's Guide to VHDLVHDL is a language for describing digital electronic systems. A vital, efficient step in the system design process, VHDL allows for the design and simulation of a hardware system prior to it actually being manufactured. Offering the same clear, accessible style as The Designer's Guide to VHDL, The Student's Guide is designed as a main text for introductory VHDL courses, and as a supplementary text for courses that require VHDL-based project work, such as computer architecture, digital design, and digital logic courses. This new condensed text also serves as a quick, self-teaching guide for practicing engineers who need to learn only the basics of VHDL. |
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1.3. rezultāts no 87.
The syntax rules for this simplified form of entity declaration are entity _
declaration = entity identifier is [ port ( port _ interface _ list ) ; ] { entity _
declarative _ item } end [ entity ] [ identifier ) ; interface _ list = ( identifier { , . . . } : [
mode ) subtype _ ...
... procedure _ call _ statement \ passive _ process _ statement } ] end [ entity ] [
identifier ) ; The difference between this and the simpler rule we have seen
before is the inclusion of the optional generic interface list before the port
interface list .
FIGURE 9 - 3 entity reg is generic ( width : positive ) ; port ( d : in bit _ vector ( O to
width - 1 ) ; q : out bit _ vector ( 0 to width - 1 ) ; clk , reset : in bit ) ; end entity reg ;
architecture behavioral of reg is begin behavior : process ( clk , reset ) is ...
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Fundamental Concepts | 1 |
Exercises | 25 |
Exercises | 51 |
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Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication Hubert Kaeslin Ierobežota priekšskatīšana - 2008 |