The Student's Guide to VHDL
Elsevier Science, 1998. gada 15. janv. - 336 lappuses
VHDL is a language for describing digital electronic systems. A vital, efficient step in the system design process, VHDL allows for the design and simulation of a hardware system prior to it actually being manufactured.
Offering the same clear, accessible style as The Designer's Guide to VHDL, The Student's Guide is designed as a main text for introductory VHDL courses, and as a supplementary text for courses that require VHDL-based project work, such as computer architecture, digital design, and digital logic courses. This new condensed text also serves as a quick, self-teaching guide for practicing engineers who need to learn only the basics of VHDL.
1.3. rezultāts no 81.
Constants and Variables An object is a named item in a VHDL model that has a
value of a specified type . ... The difference between them is that the value of a
constant cannot be changed after it is created , whereas a variable ' s value can
Constants in Package Declarations Just as we can apply the principle of
information hiding to subprograms declared in a package , we can also apply it to
constants declared in a package . The external view of a constant is just its name
FIGURE 7 - 6 package cpu _ types is constant word _ size : positive : = 16 ;
constant address _ size : positive : = 24 ; subtype word is bit _ vector ( word _ size
- 1 downto 0 ) ; subtype address is bit _ vector ( address _ size - 1 downto 0 ) ;
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