The Student's Guide to VHDL
Elsevier Science, 1998. gada 15. janv. - 336 lappuses
VHDL is a language for describing digital electronic systems. A vital, efficient step in the system design process, VHDL allows for the design and simulation of a hardware system prior to it actually being manufactured.
Offering the same clear, accessible style as The Designer's Guide to VHDL, The Student's Guide is designed as a main text for introductory VHDL courses, and as a supplementary text for courses that require VHDL-based project work, such as computer architecture, digital design, and digital logic courses. This new condensed text also serves as a quick, self-teaching guide for practicing engineers who need to learn only the basics of VHDL.
1.3. rezultāts no 90.
FIGURE 5 - 2 architecture primitive of and _ or _ inv is signal and _ a , and _ b :
bit ; signal or _ a _ b : bit ; begin and _ gate _ a : process ( a1 , a2 ) is begin and a
< = a1 and a2 ; end process and _ gate _ a ; and _ gate _ b : process ( b1 , 62 ) is
FIGURE 6 - 21 architecture arch of ent is type t is . . . ; signal s : t ; procedure p1 ( .
. . ) is variable v1 : t ; begin v1 : = s ; end procedure p1 ; begin - - arch proc1 :
process is variable v2 : t ; procedure p2 ( . . . ) is variable v3 : t ; begin p1 ( v2 , v3 ,
Figure 8 - 13 shows how the process might use the procedures to implement the
protocol . FIGURE 8 - 12 procedure init _ synchronize ( signal synch : out std _
logic ) is begin synch < = ' O ' ; end procedure init _ synchronize ; procedure
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