Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
No grāmatas satura
3. lappuse
... Several control loops with 16 or more taps are typically performed by a digital signal processor (DSP) in order to control the CD drive mechanism. Once. 3. 4 1-2 FIGURE CPU VPU0 VPU1 Memory I/O 10-channel DMAC 1.2 What are MPSoCs?
... Several control loops with 16 or more taps are typically performed by a digital signal processor (DSP) in order to control the CD drive mechanism. Once. 3. 4 1-2 FIGURE CPU VPU0 VPU1 Memory I/O 10-channel DMAC 1.2 What are MPSoCs?
3. lappuse
... loops with 16 or more taps are typically performed by a digital signal processor (DSP) in order to control the CD drive mechanism. Once 4 1-2 Image processing engine VPU1 VPU0 CPU 10-channel DMAC. 1.2 What are MPSoCs?
... loops with 16 or more taps are typically performed by a digital signal processor (DSP) in order to control the CD drive mechanism. Once 4 1-2 Image processing engine VPU1 VPU0 CPU 10-channel DMAC. 1.2 What are MPSoCs?
34. lappuse
... channel is a bundle of wires, often called a bus. To be more precise, however, a bus can be sig- nificantly more complex than a bundle of wires. On-chip busses are highly shared communication infrastructures, with complex logic blocks ...
... channel is a bundle of wires, often called a bus. To be more precise, however, a bus can be sig- nificantly more complex than a bundle of wires. On-chip busses are highly shared communication infrastructures, with complex logic blocks ...
34. lappuse
... channel is a bundle of wires, often called a bus. To be more precise, however, a bus can be significantly more complex than a bundle of wires. On-chip busses are highly shared communication infrastructures, with complex logic blocks for ...
... channel is a bundle of wires, often called a bus. To be more precise, however, a bus can be significantly more complex than a bundle of wires. On-chip busses are highly shared communication infrastructures, with complex logic blocks for ...
41. lappuse
... channels joined by programmable switches. Clusters are then connected through a generalized mesh of global long communication chan- nels. Clearly such architecture is heterogeneous because the energy cost of intra- cluster communication ...
... channels joined by programmable switches. Clusters are then connected through a generalized mesh of global long communication chan- nels. Clearly such architecture is heterogeneous because the energy cost of intra- cluster communication ...
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa