Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
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1.–5. rezultāts no 61.
xiv. lappuse
... Target Platform Architecture and Model 319 11.5 Task Concurrency Management 320 11.5.1 Global TCM Methodology 321 11.5.2 Two-Phase Scheduling Stage 321 11.5.3 Scenarios to Characterize Data-Dependent TFs 324 11.5.4 Platform Simulation ...
... Target Platform Architecture and Model 319 11.5 Task Concurrency Management 320 11.5.1 Global TCM Methodology 321 11.5.2 Two-Phase Scheduling Stage 321 11.5.3 Scenarios to Characterize Data-Dependent TFs 324 11.5.4 Platform Simulation ...
xv. lappuse
... Target Architecture Model 370 13.3.4 The Hardware/Software Wrapper Concept 370 13.4 Component-Based Design Environment 371 13.4.1 Hardware Generation 371 13.4.2 Memory Wrapper Generation 375 xvi 13.4.3 Software Wrapper Generation 378 ...
... Target Architecture Model 370 13.3.4 The Hardware/Software Wrapper Concept 370 13.4 Component-Based Design Environment 371 13.4.1 Hardware Generation 371 13.4.2 Memory Wrapper Generation 375 xvi 13.4.3 Software Wrapper Generation 378 ...
12. lappuse
... target markets. MPSoCs may use hundreds of thousands of lines of dedicated software and complex software development environments; programmers cannot use mostly low-level programming languages anymore—higher level abstractions are ...
... target markets. MPSoCs may use hundreds of thousands of lines of dedicated software and complex software development environments; programmers cannot use mostly low-level programming languages anymore—higher level abstractions are ...
22. lappuse
... component of standby power is not included in the above equation and is not a target of the techniques presented in this chapter. 2-2 IOP DSP DSP IOP Interconnectfabric D$ D$ D$ D$. 2 Techniques for Designing Energy-Aware MPSoCs.
... component of standby power is not included in the above equation and is not a target of the techniques presented in this chapter. 2-2 IOP DSP DSP IOP Interconnectfabric D$ D$ D$ D$. 2 Techniques for Designing Energy-Aware MPSoCs.
32. lappuse
... target MPSoC with four processors, utilize 4, 8, 16, or 32 banks. The rationale behind this is to reduce conflicts for a given bank. The second optimization deals with the references to the same block. When two such references occur ...
... target MPSoC with four processors, utilize 4, 8, 16, or 32 banks. The rationale behind this is to reduce conflicts for a given bank. The second optimization deals with the references to the same block. When two such references occur ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa