Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
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1.–5. rezultāts no 60.
15. lappuse
... switching, bus drivers, configuration code for the memory management unit (MMU), and interrupt service routines (ISRs). From the viewpoint of application software, the architecture provides a virtual machine on which the application ...
... switching, bus drivers, configuration code for the memory management unit (MMU), and interrupt service routines (ISRs). From the viewpoint of application software, the architecture provides a virtual machine on which the application ...
22. lappuse
... switching power. number of devices that are actually switching (drawing current from the power supply) at a given time. This definition of active power consumption illustrates the significant benefit of supply voltage scaling—a ...
... switching power. number of devices that are actually switching (drawing current from the power supply) at a given time. This definition of active power consumption illustrates the significant benefit of supply voltage scaling—a ...
25. lappuse
... switching. Thus, uniprocessor systems typically distance the digital and analog components as much as possible to reduce this effect. Whether this technique will carry over to MPSoCs, in which the ability to separate the analog and ...
... switching. Thus, uniprocessor systems typically distance the digital and analog components as much as possible to reduce this effect. Whether this technique will carry over to MPSoCs, in which the ability to separate the analog and ...
27. lappuse
... switching off the supply to idle components. An MPSoC employing such a technique will require system software that can determine the optimal scheduling of tasks on cores and can direct idle cores to switch off their supplies while ...
... switching off the supply to idle components. An MPSoC employing such a technique will require system software that can determine the optimal scheduling of tasks on cores and can direct idle cores to switch off their supplies while ...
35. lappuse
... switching activity, which is proportional to dynamic power consumption in CMOS technology. Ramprasad et al. [44] studied the data encoding for minimum switching activity problem and obtained upper and lower bounds on transition activity ...
... switching activity, which is proportional to dynamic power consumption in CMOS technology. Ramprasad et al. [44] studied the data encoding for minimum switching activity problem and obtained upper and lower bounds on transition activity ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa