Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
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1.–5. rezultāts no 68.
xi. lappuse
... Static Execution Order Scheduling 172 6.4.3 Time-Driven Scheduling 173 6.4.4 Priority-Driven Scheduling 176 6.4.5 Resource Sharing-Summary 178 6.5 Global Performance Analysis 179 6.6 Conclusions 185 7 Design of Communication ...
... Static Execution Order Scheduling 172 6.4.3 Time-Driven Scheduling 173 6.4.4 Priority-Driven Scheduling 176 6.4.5 Resource Sharing-Summary 178 6.5 Global Performance Analysis 179 6.6 Conclusions 185 7 Design of Communication ...
45. lappuse
... static, that is, the number of processors that execute the code is fixed for the entire execution. For example, if the number of processors that execute a code is fixed at eight, all parts of the code (for example, all loop nests) are ...
... static, that is, the number of processors that execute the code is fixed for the entire execution. For example, if the number of processors that execute a code is fixed at eight, all parts of the code (for example, all loop nests) are ...
53. lappuse
... static random access memory (SRAM) use a differential, precharged, low-swing signaling scheme to improve speed and energy efficiency. The transmitter is made of the precharge transistors (one for each biline), and. 53. 54 3-2 the selected ...
... static random access memory (SRAM) use a differential, precharged, low-swing signaling scheme to improve speed and energy efficiency. The transmitter is made of the precharge transistors (one for each biline), and. 53. 54 3-2 the selected ...
62. lappuse
... static memory cells. Thus, VirtexII can be also seen as an indirect network over a heterogeneous fabric. From an energy viewpoint, direct networks have the potential for being more energy efficient than shared medium networks, because ...
... static memory cells. Thus, VirtexII can be also seen as an indirect network over a heterogeneous fabric. From an energy viewpoint, direct networks have the potential for being more energy efficient than shared medium networks, because ...
69. lappuse
... static routing approach. Routing (i.e., switch programming) is performed at reconfiguration time, and routing decisions are taken on a much coarser time scale than in packetswitched networks. From a networking viewpoint, switch ...
... static routing approach. Routing (i.e., switch programming) is performed at reconfiguration time, and routing decisions are taken on a much coarser time scale than in packetswitched networks. From a networking viewpoint, switch ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa